From a0ad9a5ca52d497e2e47d2f6bec59b8b279e0ae5 Mon Sep 17 00:00:00 2001 From: Claude Date: Sat, 10 Oct 2026 08:54:06 +0000 Subject: [PATCH 1/3] ci: make the four nightly jobs actually run on nightly; skip cpu_guard under Miri The nightly-simd-polyfill, cargo-careful, docs/nightly and miri jobs run only on push / merge_group, so no PR showed them, and all four were red on master (already at 6704865): - nightly-simd-polyfill, docs, cargo-careful: dtolnay installs nightly, but rust-toolchain.toml pins stable and wins, so plain `cargo` was stable (E0554 on #![feature]; careful: target-spec-json "invalid JSON"). They now call `cargo +nightly`. - docs: `--all-features` cannot build (intel-mkl/openblas and runtime-dispatch/nightly-simd are mutually exclusive); it now uses the [package.metadata.docs.rs] set, approx,serde,rayon. - miri: cpu_guard's pre-main hook runs cpuid (inline asm), which Miri rejects, so every test binary died at --list. The hook is now cfg(not(miri)) on all three platforms, and the Miri filter skips cpu_guard:: tests. Verified locally with CI's RUSTFLAGS: the polyfill job reproduces E0554 on stable and passes with +nightly (both feature sets); the guard still fires on a normal build (v3 binary under qemu -cpu SandyBridge prints the guard message). The docs job now gets past the build and reports 127 rustdoc warnings (-Dwarnings) that it never reached before; one, a private link to DOT_I8_FOLD from #349, is fixed here, the other 126 predate this change. Co-Authored-By: Claude Opus 5.5 Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh --- .github/workflows/ci.yaml | 16 ++++++++++++---- scripts/miri-tests.sh | 8 +++++++- src/cpu_guard.rs | 10 +++++++--- src/simd_avx.rs | 2 +- src/simd_avx2.rs | 2 +- 5 files changed, 28 insertions(+), 10 deletions(-) diff --git a/.github/workflows/ci.yaml b/.github/workflows/ci.yaml index e960d9ee..c7837fc2 100644 --- a/.github/workflows/ci.yaml +++ b/.github/workflows/ci.yaml @@ -342,9 +342,11 @@ jobs: - uses: dtolnay/rust-toolchain@nightly - uses: Swatinem/rust-cache@v2 - name: cargo check (nightly + nightly-simd feature) - run: cargo check -p ndarray --features approx,serde,rayon,nightly-simd + # `+nightly`: rust-toolchain.toml pins stable and takes precedence over + # the toolchain dtolnay installs, so a plain `cargo` here is stable. + run: cargo +nightly check -p ndarray --features approx,serde,rayon,nightly-simd - name: cargo check (nightly + nightly-simd + hpc-extras) - run: cargo check -p ndarray --features approx,serde,rayon,nightly-simd,hpc-extras + run: cargo +nightly check -p ndarray --features approx,serde,rayon,nightly-simd,hpc-extras blas-msrv: runs-on: ubuntu-latest @@ -422,7 +424,9 @@ jobs: - uses: taiki-e/install-action@nextest - name: Install cargo-careful run: cargo install cargo-careful - - run: cargo careful nextest run -Zcareful-sanitizer --features="$FEATURES" + # `+nightly`: see nightly-simd-polyfill. On stable, careful fails at + # `rustc --print target-spec-json` ("output is invalid JSON"). + - run: cargo +nightly careful nextest run -Zcareful-sanitizer --features="$FEATURES" docs: # Nightly needed for --cfg docsrs. Only on merge queue / push. @@ -434,7 +438,11 @@ jobs: steps: - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@nightly - - run: cargo doc --no-deps --all-features + # `+nightly`: see nightly-simd-polyfill. Features match + # `[package.metadata.docs.rs]`: `--all-features` cannot build, because + # `intel-mkl`/`openblas` and `runtime-dispatch`/`nightly-simd` are + # mutually exclusive (`compile_error!`). + - run: cargo +nightly doc --no-deps --features approx,serde,rayon conclusion: needs: diff --git a/scripts/miri-tests.sh b/scripts/miri-tests.sh index 0f3a7d9d..f39a48b0 100755 --- a/scripts/miri-tests.sh +++ b/scripts/miri-tests.sh @@ -64,9 +64,10 @@ cargo +nightly miri nextest run -v \ test(/^hpc::/) - test(/^hpc::byte_scan/) ) and !test(/^simd::tests::/) and !test(/^hpc::framebuffer::pyramid_tests::/) + and !test(/^cpu_guard::/) ' # -# Filter rationale (3-clause AND): +# Filter rationale (4-clause AND): # # 1. `!(test(/^hpc::/) - test(/^hpc::byte_scan/))` # Skip everything in `hpc::*` EXCEPT `hpc::byte_scan` (the scalar-fallback @@ -85,3 +86,8 @@ cargo +nightly miri nextest run -v \ # loops over SIMD-shaped data). Not a UB signal — pure runtime cost. # Re-enable once the test fixtures are sized down or the loops are # cfg(miri)-shortened. +# +# 4. `!test(/^cpu_guard::/)` +# `cpu_guard` reads the CPU with `cpuid`, which is inline assembly; Miri +# rejects it ("inline assembly is not supported"). The pre-`main` hook is +# `cfg(not(miri))` for the same reason, so test binaries start under Miri. diff --git a/src/cpu_guard.rs b/src/cpu_guard.rs index 547d67ee..f34fca3b 100644 --- a/src/cpu_guard.rs +++ b/src/cpu_guard.rs @@ -348,6 +348,10 @@ pub fn assert_build_cpu() { /// The pre-`main` hook. Prints and exits instead of panicking: unwinding out /// of a loader-invoked `extern "C"` function would abort with no message. +/// +/// Not installed under Miri: `cpuid` is inline assembly, which Miri cannot +/// execute, and an interpreter has no CPU to check. +#[cfg(not(miri))] extern "C" fn guard_before_main() { if let Err(mismatch) = check_build_cpu() { use std::io::Write; @@ -358,17 +362,17 @@ extern "C" fn guard_before_main() { // The loader calls every function pointer in these sections before `main`. // `#[used]` keeps the static even though nothing references it. -#[cfg(any(target_os = "linux", target_os = "android", target_os = "freebsd"))] +#[cfg(all(not(miri), any(target_os = "linux", target_os = "android", target_os = "freebsd")))] #[used] #[link_section = ".init_array"] static GUARD_BEFORE_MAIN: extern "C" fn() = guard_before_main; -#[cfg(any(target_os = "macos", target_os = "ios"))] +#[cfg(all(not(miri), any(target_os = "macos", target_os = "ios")))] #[used] #[link_section = "__DATA,__mod_init_func"] static GUARD_BEFORE_MAIN: extern "C" fn() = guard_before_main; -#[cfg(target_os = "windows")] +#[cfg(all(not(miri), target_os = "windows"))] #[used] #[link_section = ".CRT$XCU"] static GUARD_BEFORE_MAIN: extern "C" fn() = guard_before_main; diff --git a/src/simd_avx.rs b/src/simd_avx.rs index 77657c7a..884c0a5c 100644 --- a/src/simd_avx.rs +++ b/src/simd_avx.rs @@ -124,7 +124,7 @@ pub fn popcount(a: &[u8]) -> u64 { /// `min(a.len(), b.len())` bytes. SSE4.1 `pmovsxbw` sign-extends each 16-byte /// chunk to i16 and SSE2 `pmaddwd` multiplies pairwise into i32, exact for /// every i8 pair; the i32 lanes are folded into an i64 every -/// [`crate::simd_avx2::DOT_I8_FOLD`] chunks, so no length can wrap them. +/// `crate::simd_avx2::DOT_I8_FOLD` chunks, so no length can wrap them. pub fn dot_i8(a: &[u8], b: &[u8]) -> i64 { let len = a.len().min(b.len()); let (a, b) = (&a[..len], &b[..len]); diff --git a/src/simd_avx2.rs b/src/simd_avx2.rs index ff8bb795..19622d4e 100644 --- a/src/simd_avx2.rs +++ b/src/simd_avx2.rs @@ -415,7 +415,7 @@ pub fn popcount(a: &[u8]) -> u64 { /// /// Each 32-byte chunk is sign-extended to i16 (`vpmovsxbw`) and multiplied /// pairwise into i32 (`vpmaddwd`), which is exact for every i8 pair. The i32 -/// lanes are folded into an i64 every [`DOT_I8_FOLD`] chunks, so no input +/// lanes are folded into an i64 every `DOT_I8_FOLD` chunks, so no input /// length can wrap them. (The earlier `vpmaddubsw` form saturated i16 at /// `a = b = 127`, and read `b` past its end when `b` was the shorter slice.) pub fn dot_i8(a: &[u8], b: &[u8]) -> i64 { From a1b80556c3ac093000bb3e6c749eeb68579b3aeb Mon Sep 17 00:00:00 2001 From: Claude Date: Sat, 10 Oct 2026 08:59:42 +0000 Subject: [PATCH 2/3] docs: fix the 126 rustdoc warnings so docs/nightly passes with -Dwarnings The docs job never reached rustdoc before (it failed at the build), so these had accumulated unseen. Doc-comment lines only; no code changes. - 104 index expressions in prose (`a[i]`, `[768]`, `self[k]`) parsed as intra-doc links: brackets escaped (`\[i\]`, renders identically). Fenced code blocks are left untouched. - 7 chained forms (`basis_cos[f][j]`, byte layouts like `[name_len:u32][name]...`): put in code spans. - 9 links to private items: kept as code spans without the link. - 7 unclosed HTML tags (`Vec`, `LazyLock`): put in code spans. - Paths fixed: crate::hpc::quantized::int8_gemm_i32, the soa_struct! and blocked_grid_struct! macros (crate::), BlockedGrid::{new, new_with_pad, idx}, blas_rotg; jitson_cranelift (feature jit-native) is now unlinked; one redundant link target simplified. Verified: RUSTDOCFLAGS="-Dwarnings --cfg docsrs" cargo +nightly doc --no-deps --features approx,serde,rayon exits 0 (was 127 warnings); every changed line is a /// or //! line; clippy v3 and fmt clean. Co-Authored-By: Claude Opus 5.5 Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh --- src/backend/kernels_avx512.rs | 10 +++---- src/backend/native.rs | 16 +++++----- src/bitwise.rs | 2 +- src/heel_f64x8.rs | 4 +-- src/hpc/amx_matmul.rs | 2 +- src/hpc/amx_ops.rs | 36 +++++++++++------------ src/hpc/audio/mdct.rs | 2 +- src/hpc/audio/modes.rs | 6 ++-- src/hpc/audio/voice.rs | 2 +- src/hpc/bgz17_bridge.rs | 6 ++-- src/hpc/blas_level1.rs | 8 ++--- src/hpc/blocked_grid/base.rs | 12 ++++---- src/hpc/blocked_grid/grid_struct_macro.rs | 2 +- src/hpc/bnn_causal_trajectory.rs | 6 ++-- src/hpc/clam_compress.rs | 4 +-- src/hpc/entropy_ladder.rs | 2 +- src/hpc/framebuffer.rs | 2 +- src/hpc/gguf_indexer.rs | 6 ++-- src/hpc/gpt2/weights.rs | 12 ++++---- src/hpc/holo.rs | 14 ++++----- src/hpc/jina/runtime.rs | 2 +- src/hpc/jitson/mod.rs | 2 +- src/hpc/linalg/svd.rs | 2 +- src/hpc/merkle_tree.rs | 4 +-- src/hpc/models/safetensors.rs | 4 +-- src/hpc/openchat/weights.rs | 6 ++-- src/hpc/renderer.rs | 2 +- src/hpc/safetensors.rs | 2 +- src/hpc/signature_pde.rs | 2 +- src/hpc/soa.rs | 2 +- src/hpc/surround_metadata.rs | 2 +- src/hpc/vnni_gemm.rs | 2 +- src/palette_codec.rs | 2 +- src/simd.rs | 4 +-- src/simd_amx.rs | 4 +-- src/simd_avx2.rs | 4 +-- src/simd_avx512.rs | 14 ++++----- src/simd_int_ops.rs | 2 +- src/simd_masking_ops.rs | 10 +++---- src/simd_neon.rs | 6 ++-- src/simd_nightly/_original_draft.rs | 2 +- src/simd_nightly/masks.rs | 8 ++--- src/simd_wasm.rs | 2 +- 43 files changed, 122 insertions(+), 122 deletions(-) diff --git a/src/backend/kernels_avx512.rs b/src/backend/kernels_avx512.rs index 5e3963f5..d0f27333 100644 --- a/src/backend/kernels_avx512.rs +++ b/src/backend/kernels_avx512.rs @@ -21,7 +21,7 @@ use crate::simd::{F32x16, F64x8}; // BLAS Level 1 — 12 functions (compat types) // ═══════════════════════════════════════════════════════════════════ -/// Dot product: sum(x[i] * y[i]) using 4x-unrolled FMA. +/// Dot product: sum(x\[i\] * y\[i\]) using 4x-unrolled FMA. /// # Safety /// Caller must ensure AVX-512F is available (`simd_caps().avx512f`). #[cfg(target_arch = "x86_64")] @@ -167,7 +167,7 @@ pub fn scal_f64(alpha: f64, x: &mut [f64]) { } } -/// L1 norm: sum(|x[i]|) (f32, 16-wide). +/// L1 norm: sum(|x\[i\]|) (f32, 16-wide). /// # Safety /// Caller must ensure AVX-512F is available (`simd_caps().avx512f`). #[cfg(target_arch = "x86_64")] @@ -185,7 +185,7 @@ pub fn asum_f32(x: &[f32]) -> f32 { sum } -/// L1 norm: sum(|x[i]|) (f64, 8-wide). +/// L1 norm: sum(|x\[i\]|) (f64, 8-wide). /// # Safety /// Caller must ensure AVX-512F is available (`simd_caps().avx512f`). #[cfg(target_arch = "x86_64")] @@ -203,7 +203,7 @@ pub fn asum_f64(x: &[f64]) -> f64 { sum } -/// L2 norm: sqrt(sum(x[i]^2)) (f32, 16-wide FMA). +/// L2 norm: sqrt(sum(x\[i\]^2)) (f32, 16-wide FMA). /// # Safety /// Caller must ensure AVX-512F is available (`simd_caps().avx512f`). #[cfg(target_arch = "x86_64")] @@ -225,7 +225,7 @@ pub fn nrm2_f32(x: &[f32]) -> f32 { sum.sqrt() } -/// L2 norm: sqrt(sum(x[i]^2)) (f64, 8-wide FMA). +/// L2 norm: sqrt(sum(x\[i\]^2)) (f64, 8-wide FMA). /// # Safety /// Caller must ensure AVX-512F is available (`simd_caps().avx512f`). #[cfg(target_arch = "x86_64")] diff --git a/src/backend/native.rs b/src/backend/native.rs index 42559c2d..7a5260d8 100644 --- a/src/backend/native.rs +++ b/src/backend/native.rs @@ -167,10 +167,10 @@ macro_rules! dispatch { // ─── BLAS-1 dispatch ────────────────────────────────────────────── dispatch!( - /// Dot product: result = sum(x[i] * y[i]) (f32). + /// Dot product: result = sum(x\[i\] * y\[i\]) (f32). dot_f32(x: &[f32], y: &[f32]) -> f32); dispatch!( - /// Dot product: result = sum(x[i] * y[i]) (f64). + /// Dot product: result = sum(x\[i\] * y\[i\]) (f64). dot_f64(x: &[f64], y: &[f64]) -> f64); dispatch!( /// AXPY: y = alpha * x + y (f32). @@ -186,16 +186,16 @@ dispatch!( /// Scale: x = alpha * x (f64). scal_f64(alpha: f64, x: &mut [f64])); dispatch!( - /// L2 norm: sqrt(sum(x[i]^2)) (f32). + /// L2 norm: sqrt(sum(x\[i\]^2)) (f32). nrm2_f32(x: &[f32]) -> f32); dispatch!( - /// L2 norm: sqrt(sum(x[i]^2)) (f64). + /// L2 norm: sqrt(sum(x\[i\]^2)) (f64). nrm2_f64(x: &[f64]) -> f64); dispatch!( - /// L1 norm: sum(|x[i]|) (f32). + /// L1 norm: sum(|x\[i\]|) (f32). asum_f32(x: &[f32]) -> f32); dispatch!( - /// L1 norm: sum(|x[i]|) (f64). + /// L1 norm: sum(|x\[i\]|) (f64). asum_f64(x: &[f64]) -> f64); // ─── GEMM dispatch ─────────────────────────────────────────────── @@ -284,7 +284,7 @@ pub fn gemm_f64( /// GEMV: y = alpha * A * x + beta * y (f32, row-major). /// /// SIMD tiers compute each row via [`dot_f32`]; the scalar tier uses -/// the byte-stable [`scalar::gemv_f32`] reference. +/// the byte-stable `scalar::gemv_f32` reference. pub fn gemv_f32(m: usize, n: usize, alpha: f32, a: &[f32], lda: usize, x: &[f32], beta: f32, y: &mut [f32]) { if m == 0 { return; // no rows ⇒ no-op; must not slice `x[..n]` (scalar ref returns too) @@ -307,7 +307,7 @@ pub fn gemv_f32(m: usize, n: usize, alpha: f32, a: &[f32], lda: usize, x: &[f32] /// GEMV: y = alpha * A * x + beta * y (f64, row-major). /// /// SIMD tiers compute each row via [`dot_f64`]; the scalar tier uses -/// the byte-stable [`scalar::gemv_f64`] reference. +/// the byte-stable `scalar::gemv_f64` reference. pub fn gemv_f64(m: usize, n: usize, alpha: f64, a: &[f64], lda: usize, x: &[f64], beta: f64, y: &mut [f64]) { if m == 0 { return; // no rows ⇒ no-op; must not slice `x[..n]` (scalar ref returns too) diff --git a/src/bitwise.rs b/src/bitwise.rs index ebc7d931..9be65147 100644 --- a/src/bitwise.rs +++ b/src/bitwise.rs @@ -204,7 +204,7 @@ const HAMMING_WITHIN_BLOCK: usize = 256; /// /// Exact, not approximate: the running total only grows, so once it exceeds /// `max` the final distance must too, and the remaining bytes are skipped. -/// The check happens after every [`HAMMING_WITHIN_BLOCK`]-byte block, so a +/// The check happens after every `HAMMING_WITHIN_BLOCK`-byte block, so a /// reject costs at most one block beyond the point where the budget ran out. /// Like [`hamming_distance_raw`], unequal lengths measure the common prefix. /// diff --git a/src/heel_f64x8.rs b/src/heel_f64x8.rs index 9fd79540..6abab481 100644 --- a/src/heel_f64x8.rs +++ b/src/heel_f64x8.rs @@ -15,7 +15,7 @@ use crate::simd::{array_chunks, F64x8}; /// /// `distances[i]` = distance for HEEL plane i. /// `weights[i]` = importance weight for plane i. -/// Returns: Σ(distances[i] × weights[i]). +/// Returns: Σ(distances\[i\] × weights\[i\]). /// /// One F64x8 multiply + reduce_sum. On AVX-512: single vmulpd + vreducepd. /// On AVX2: 2× vmulpd + 2× haddpd. Scalar: 8 multiplies + sum. @@ -28,7 +28,7 @@ pub fn heel_weighted_distance(distances: &[f64; 8], weights: &[f64; 8]) -> f64 { /// Compute L1-like distance across 8 HEEL planes. /// -/// For each plane i: distance[i] = popcount(a[i] XOR b[i]) as f64. +/// For each plane i: distance\[i\] = popcount(a\[i\] XOR b\[i\]) as f64. /// This is Hamming on binary HEEL planes — valid because HEEL planes /// ARE uniform binary data (unlike bgz17 i16 which must use L1). pub fn heel_plane_distances(a: &[u64; 8], b: &[u64; 8]) -> [f64; 8] { diff --git a/src/hpc/amx_matmul.rs b/src/hpc/amx_matmul.rs index b483f2a3..65abadfd 100644 --- a/src/hpc/amx_matmul.rs +++ b/src/hpc/amx_matmul.rs @@ -81,7 +81,7 @@ impl TileConfig { /// register-blocked int8 kernel: tmm0-3 = the four C accumulators, tmm4-5 = /// two plain A row-blocks (rm/unsigned), tmm6-7 = two VNNI B col-blocks /// (vvvv/signed). Every tile is 16×64 so one config serves all roles. Same - /// XTILECFG layout as [`Self::for_dpbusd`]: colsb[t] u16 @ 16+2t, rows[t] + /// XTILECFG layout as [`Self::for_dpbusd`]: colsb\[t\] u16 @ 16+2t, rows\[t\] /// u8 @ 48+t. /// /// # Examples diff --git a/src/hpc/amx_ops.rs b/src/hpc/amx_ops.rs index 390fa903..fe36556e 100644 --- a/src/hpc/amx_ops.rs +++ b/src/hpc/amx_ops.rs @@ -34,15 +34,15 @@ //! //! | tier | ops | CPUID | first silicon | //! |---|---|---|---| -//! | AMX-TILE | config, zero, load/store, release | 7.0:EDX[24] | Sapphire Rapids | -//! | AMX-INT8 | `tdpb{ss,su,us,uu}d` | 7.0:EDX[25] | Sapphire Rapids | -//! | AMX-BF16 | `tdpbf16ps` | 7.0:EDX[22] | Sapphire Rapids | -//! | AMX-FP16 | `tdpfp16ps` | 7.1:EAX[21] | Granite Rapids | -//! | AMX-COMPLEX | `tcmm{im,rl}fp16ps` | 7.1:EDX[8] | Granite Rapids-D | -//! | AMX-FP8 | `tdp{b,bh,hb,h}f8ps` | 1E.1:EAX[4] | Diamond Rapids | -//! | AMX-TF32 | `tmmultf32ps` | 1E.1:EAX[6] | Diamond Rapids (see note) | -//! | AMX-AVX512 | `tcvtrow*`, `tilemovrow` | 1E.1:EAX[7] | Diamond Rapids | -//! | AMX-MOVRS | `tileloaddrs{,t1}` | 1E.1:EAX[8] | Diamond Rapids | +//! | AMX-TILE | config, zero, load/store, release | 7.0:EDX\[24\] | Sapphire Rapids | +//! | AMX-INT8 | `tdpb{ss,su,us,uu}d` | 7.0:EDX\[25\] | Sapphire Rapids | +//! | AMX-BF16 | `tdpbf16ps` | 7.0:EDX\[22\] | Sapphire Rapids | +//! | AMX-FP16 | `tdpfp16ps` | 7.1:EAX\[21\] | Granite Rapids | +//! | AMX-COMPLEX | `tcmm{im,rl}fp16ps` | 7.1:EDX\[8\] | Granite Rapids-D | +//! | AMX-FP8 | `tdp{b,bh,hb,h}f8ps` | 1E.1:EAX\[4\] | Diamond Rapids | +//! | AMX-TF32 | `tmmultf32ps` | 1E.1:EAX\[6\] | Diamond Rapids (see note) | +//! | AMX-AVX512 | `tcvtrow*`, `tilemovrow` | 1E.1:EAX\[7\] | Diamond Rapids | +//! | AMX-MOVRS | `tileloaddrs{,t1}` | 1E.1:EAX\[8\] | Diamond Rapids | //! //! Note on TF32: LLVM `main` has removed `amx-tf32` (and `amx-transpose`) //! from both the assembler and `Host.cpp`. The 22.1.8 assembler in the @@ -655,23 +655,23 @@ tile_row_to_zmm!( /// and gates the INT8 ops. This struct answers "which ops exist once I may". #[derive(Copy, Clone, Debug, PartialEq, Eq, Default)] pub struct AmxFeatures { - /// AMX-TILE (7.0:EDX[24]). + /// AMX-TILE (7.0:EDX\[24\]). pub tile: bool, - /// AMX-INT8 (7.0:EDX[25]). + /// AMX-INT8 (7.0:EDX\[25\]). pub int8: bool, - /// AMX-BF16 (7.0:EDX[22]). + /// AMX-BF16 (7.0:EDX\[22\]). pub bf16: bool, - /// AMX-FP16 (7.1:EAX[21]). + /// AMX-FP16 (7.1:EAX\[21\]). pub fp16: bool, - /// AMX-COMPLEX (7.1:EDX[8]). + /// AMX-COMPLEX (7.1:EDX\[8\]). pub complex: bool, - /// AMX-FP8 (1E.1:EAX[4]). + /// AMX-FP8 (1E.1:EAX\[4\]). pub fp8: bool, - /// AMX-TF32 (1E.1:EAX[6]; the bit LLVM used before dropping the feature). + /// AMX-TF32 (1E.1:EAX\[6\]; the bit LLVM used before dropping the feature). pub tf32: bool, - /// AMX-AVX512 (1E.1:EAX[7]). + /// AMX-AVX512 (1E.1:EAX\[7\]). pub avx512: bool, - /// AMX-MOVRS (1E.1:EAX[8]). + /// AMX-MOVRS (1E.1:EAX\[8\]). pub movrs: bool, } diff --git a/src/hpc/audio/mdct.rs b/src/hpc/audio/mdct.rs index e80c9dc4..48343e5c 100644 --- a/src/hpc/audio/mdct.rs +++ b/src/hpc/audio/mdct.rs @@ -18,7 +18,7 @@ pub const FRAME_SIZE: usize = 960; pub const MDCT_SIZE: usize = FRAME_SIZE / 2; /// Sine window for MDCT (Opus uses a sine window for CELT mode). -/// w[n] = sin(π/N × (n + 0.5)) +/// w\[n\] = sin(π/N × (n + 0.5)) pub fn sine_window(n: usize) -> Vec { (0..n) .map(|i| (PI / n as f32 * (i as f32 + 0.5)).sin()) diff --git a/src/hpc/audio/modes.rs b/src/hpc/audio/modes.rs index a76e5cd4..dec373bc 100644 --- a/src/hpc/audio/modes.rs +++ b/src/hpc/audio/modes.rs @@ -290,9 +290,9 @@ impl OctaveBand { /// Build from a fundamental frequency. /// /// The pattern captures the harmonic envelope at that frequency: - /// pattern[0] = fundamental energy weight - /// pattern[1] = 2nd harmonic weight - /// pattern[2] = 3rd harmonic weight + /// pattern\[0\] = fundamental energy weight + /// pattern\[1\] = 2nd harmonic weight + /// pattern\[2\] = 3rd harmonic weight /// /// The harmonic decay rate determines voice character: /// steep decay → flute/sine (pure tone) diff --git a/src/hpc/audio/voice.rs b/src/hpc/audio/voice.rs index 6539f541..ca554666 100644 --- a/src/hpc/audio/voice.rs +++ b/src/hpc/audio/voice.rs @@ -84,7 +84,7 @@ impl VoiceArchetype { /// via strided sampling + quantization. /// /// The stride determines which embedding dimensions map to which channels: - /// dim[0], dim[stride], dim[2*stride], ... → channels 0..15 + /// dim\[0\], dim\[stride\], dim\[2*stride\], ... → channels 0..15 pub fn from_embedding(embedding: &[f32], stride: usize) -> Self { let mut channels = [0i8; N_VOICE_CHANNELS]; diff --git a/src/hpc/bgz17_bridge.rs b/src/hpc/bgz17_bridge.rs index cf44dd8e..54c3e509 100644 --- a/src/hpc/bgz17_bridge.rs +++ b/src/hpc/bgz17_bridge.rs @@ -1,6 +1,6 @@ //! Bridge between ndarray Fingerprint<256> (2KB) and Base17 (34 bytes). //! -//! Converts flat 16384-bit fingerprint planes to i16[17] base patterns +//! Converts flat 16384-bit fingerprint planes to i16\[17\] base patterns //! using golden-step octave averaging. //! //! This is a self-contained port of the bgz17 crate's `base17` module, @@ -376,7 +376,7 @@ impl Base17 { /// Byte size of serialized form. pub const BYTE_SIZE: usize = BASE_DIM * 2; // 34 - /// Encode i8[16384] accumulator into a Base17 pattern. + /// Encode i8\[16384\] accumulator into a Base17 pattern. /// /// For each of 17 base dimensions, averages the accumulator values at /// golden-step-selected positions across all octaves, then scales by @@ -527,7 +527,7 @@ impl SpoBase17 { /// Byte size of serialized form. pub const BYTE_SIZE: usize = Base17::BYTE_SIZE * 3; // 102 - /// Encode three i8[16384] accumulator planes. + /// Encode three i8\[16384\] accumulator planes. pub fn encode(s: &[i8], p: &[i8], o: &[i8]) -> Self { SpoBase17 { subject: Base17::encode(s), diff --git a/src/hpc/blas_level1.rs b/src/hpc/blas_level1.rs index 7bdafc07..7fb08e1c 100644 --- a/src/hpc/blas_level1.rs +++ b/src/hpc/blas_level1.rs @@ -19,7 +19,7 @@ use crate::imp_prelude::*; /// assert!((x.blas_dot(&y) - 32.0).abs() < 1e-5); /// ``` pub trait BlasLevel1 { - /// Dot product: Σ x[i] * y[i] + /// Dot product: Σ x\[i\] * y\[i\] fn blas_dot(&self, other: &Self) -> A; /// AXPY: self = alpha * other + self (modifies self in-place) @@ -28,10 +28,10 @@ pub trait BlasLevel1 { /// Scale: self = alpha * self fn blas_scal(&mut self, alpha: A); - /// L2 norm: sqrt(Σ self[i]²) + /// L2 norm: sqrt(Σ self\[i\]²) fn blas_nrm2(&self) -> A; - /// L1 norm (absolute sum): Σ |self[i]| + /// L1 norm (absolute sum): Σ |self\[i\]| fn blas_asum(&self) -> A; /// Index of maximum absolute value element. @@ -118,7 +118,7 @@ where /// Givens rotation parameters. /// -/// Returned by [`blas_rotg`](GivensRotation::blas_rotg). Contains the cosine +/// Returned by [`blas_rotg`]. Contains the cosine /// and sine of the rotation that zeroes out the second component. #[derive(Clone, Copy, Debug)] pub struct GivensRotation { diff --git a/src/hpc/blocked_grid/base.rs b/src/hpc/blocked_grid/base.rs index ee4fbd18..57c875fb 100644 --- a/src/hpc/blocked_grid/base.rs +++ b/src/hpc/blocked_grid/base.rs @@ -192,10 +192,10 @@ impl BlockedGrid { /// The returned slice **includes padding cells** at the right and bottom /// of the logical extent. The slice length is `padded_rows() * padded_cols()`, /// not `rows() * cols()`. Cells at indices that map outside the logical - /// (rows, cols) box are padding cells (default-initialized via [`new`] or - /// set explicitly via [`new_with_pad`]). + /// (rows, cols) box are padding cells (default-initialized via [`new`](BlockedGrid::new) or + /// set explicitly via [`new_with_pad`](BlockedGrid::new_with_pad)). /// - /// To compute a logical-cell flat index correctly, use [`idx`]: + /// To compute a logical-cell flat index correctly, use [`idx`](BlockedGrid::idx): /// `as_padded_slice()[grid.idx(r, c)]`. NEVER index the slice as /// `r * cols() + c` — that ignores stride and reads the wrong cell. /// @@ -219,10 +219,10 @@ impl BlockedGrid { /// The returned slice **includes padding cells** at the right and bottom /// of the logical extent. The slice length is `padded_rows() * padded_cols()`, /// not `rows() * cols()`. Cells at indices that map outside the logical - /// (rows, cols) box are padding cells (default-initialized via [`new`] or - /// set explicitly via [`new_with_pad`]). + /// (rows, cols) box are padding cells (default-initialized via [`new`](BlockedGrid::new) or + /// set explicitly via [`new_with_pad`](BlockedGrid::new_with_pad)). /// - /// To compute a logical-cell flat index correctly, use [`idx`]: + /// To compute a logical-cell flat index correctly, use [`idx`](BlockedGrid::idx): /// `as_padded_slice_mut()[grid.idx(r, c)]`. NEVER index the slice as /// `r * cols() + c` — that ignores stride and reads the wrong cell. /// diff --git a/src/hpc/blocked_grid/grid_struct_macro.rs b/src/hpc/blocked_grid/grid_struct_macro.rs index 093e85e6..2ad8fa12 100644 --- a/src/hpc/blocked_grid/grid_struct_macro.rs +++ b/src/hpc/blocked_grid/grid_struct_macro.rs @@ -85,7 +85,7 @@ use crate::hpc::blocked_grid::BlockedGrid; /// Object-safe trait that exposes the dimension accessors of a /// `BlockedGrid` without naming the element type. /// -/// Returned by [`blocked_grid_struct!`]-generated `field_n::()` accessors. +/// Returned by [`blocked_grid_struct!`](crate::blocked_grid_struct)-generated `field_n::()` accessors. /// Useful for code that needs to inspect or assert grid dimensions uniformly /// across all fields of a SoA-of-grids struct without monomorphizing on the /// element type. diff --git a/src/hpc/bnn_causal_trajectory.rs b/src/hpc/bnn_causal_trajectory.rs index 70b5715f..59a97d7a 100644 --- a/src/hpc/bnn_causal_trajectory.rs +++ b/src/hpc/bnn_causal_trajectory.rs @@ -141,11 +141,11 @@ pub struct ResonatorSnapshot { pub o_mask: Vec, /// Number of codebook entries. pub n_entries: usize, - /// Convergence delta: Hamming(s_est[t], s_est[t-1]). + /// Convergence delta: Hamming(s_est\[t\], s_est[t-1]). pub delta_s: u32, - /// Convergence delta: Hamming(p_est[t], p_est[t-1]). + /// Convergence delta: Hamming(p_est\[t\], p_est[t-1]). pub delta_p: u32, - /// Convergence delta: Hamming(o_est[t], o_est[t-1]). + /// Convergence delta: Hamming(o_est\[t\], o_est[t-1]). pub delta_o: u32, } diff --git a/src/hpc/clam_compress.rs b/src/hpc/clam_compress.rs index e6949983..6da3ecf7 100644 --- a/src/hpc/clam_compress.rs +++ b/src/hpc/clam_compress.rs @@ -35,7 +35,7 @@ //! //! To reconstruct x from encoding + center: //! 1. Start with a copy of center -//! 2. Apply each (pos, val): result[pos] = val +//! 2. Apply each (pos, val): result\[pos\] = val //! //! For Hamming distance search, we can compute d(query, x) from the //! encoding without full decompression: @@ -158,7 +158,7 @@ pub struct CompressedTree { pub encodings: Vec, /// Which center each point is encoded relative to. - /// encodings[i] + center_data[encoding_centers[i]] = original point i. + /// encodings\[i\] + center_data[encoding_centers\[i\]] = original point i. pub encoding_centers: Vec, /// Per-cluster compression decisions. diff --git a/src/hpc/entropy_ladder.rs b/src/hpc/entropy_ladder.rs index ad58bae2..61b8c40f 100644 --- a/src/hpc/entropy_ladder.rs +++ b/src/hpc/entropy_ladder.rs @@ -281,7 +281,7 @@ pub enum ForkAction { } /// The fork decision. `challenge = residue_surprise(residue_mag, noise_floor, -/// sigma_k)`; `in_domain_skill ∈ [0,1]` is the codebook's remaining resolving +/// sigma_k)`; `in_domain_skill ∈ \[0,1\]` is the codebook's remaining resolving /// capacity. The challenge↔skill delta `δ` is banded on the shipped /// `flow_state_from` boundaries — **Anxiety `δ>0.2`** and **Boredom `δ<-0.2`** — /// then HHTL depth decides descend-vs-fork. The matched middle (`-0.2 ≤ δ ≤ 0.2`, diff --git a/src/hpc/framebuffer.rs b/src/hpc/framebuffer.rs index 5c9a4323..392360ad 100644 --- a/src/hpc/framebuffer.rs +++ b/src/hpc/framebuffer.rs @@ -654,7 +654,7 @@ impl FireState { // (7 rows each). Total atlas: 95 × 5 = 475 bytes — fits in L1. // ───────────────────────────────────────────────────────────────────── -/// 5×7 bitmap glyph for one character. Column-major: glyph[col] has 7 bits (rows). +/// 5×7 bitmap glyph for one character. Column-major: glyph\[col\] has 7 bits (rows). pub type Glyph = [u8; 5]; /// Minimal 5×7 ASCII glyph set. Covers A-Z, 0-9, space, common punctuation. diff --git a/src/hpc/gguf_indexer.rs b/src/hpc/gguf_indexer.rs index a453cf4d..146eadf5 100644 --- a/src/hpc/gguf_indexer.rs +++ b/src/hpc/gguf_indexer.rs @@ -399,7 +399,7 @@ pub fn stream_index_gguf_bf16( /// /// The header must have: /// - `tensor_data_offset`: absolute byte offset where tensor data starts -/// - `tensors`: Vec with name, dimensions, dtype, offset (relative to data start) +/// - `tensors`: `Vec` with name, dimensions, dtype, offset (relative to data start) pub fn stream_index_gguf_bf16_with_header( reader: &mut R, writer: &mut W, header: &gguf::GgufFile, octave_stride: usize, callback: Option<&dyn Fn(&str, &LayerType, usize, usize)>, @@ -605,7 +605,7 @@ impl CompressedTensor { self.original_bytes() as f64 / self.compressed_bytes() as f64 } - /// Serialize to bytes: [name_len:u32][name][layer_type:u8][n_rows:u32][n_cols:u32][base17 × n_rows] + /// Serialize to bytes: `[name_len:u32][name][layer_type:u8][n_rows:u32][n_cols:u32][base17 × n_rows]` pub fn write_to(&self, w: &mut W) -> Result<(), String> { let name_bytes = self.name.as_bytes(); w.write_all(&(name_bytes.len() as u32).to_le_bytes()) @@ -632,7 +632,7 @@ impl CompressedTensor { Ok(()) } - /// Deserialize from bytes: [name_len:u32][name][layer_type:u8][n_rows:u32][n_cols:u32][base17 × n_rows] + /// Deserialize from bytes: `[name_len:u32][name][layer_type:u8][n_rows:u32][n_cols:u32][base17 × n_rows]` pub fn read_from(r: &mut R) -> Result { let mut u32_buf = [0u8; 4]; diff --git a/src/hpc/gpt2/weights.rs b/src/hpc/gpt2/weights.rs index 23a2d651..99adb217 100644 --- a/src/hpc/gpt2/weights.rs +++ b/src/hpc/gpt2/weights.rs @@ -18,22 +18,22 @@ pub const MAX_SEQ_LEN: usize = 1024; /// All weights for one transformer layer. #[derive(Clone)] pub struct LayerWeights { - /// Attention layer norm: weight [768] + bias [768] + /// Attention layer norm: weight \[768\] + bias \[768\] pub ln1_weight: Vec, pub ln1_bias: Vec, - /// Combined Q/K/V projection: [768, 2304] + bias [2304] + /// Combined Q/K/V projection: [768, 2304] + bias \[2304\] pub attn_qkv_weight: Vec, pub attn_qkv_bias: Vec, - /// Output projection: [768, 768] + bias [768] + /// Output projection: [768, 768] + bias \[768\] pub attn_out_weight: Vec, pub attn_out_bias: Vec, - /// MLP layer norm: weight [768] + bias [768] + /// MLP layer norm: weight \[768\] + bias \[768\] pub ln2_weight: Vec, pub ln2_bias: Vec, - /// MLP fc: [768, 3072] + bias [3072] + /// MLP fc: [768, 3072] + bias \[3072\] pub mlp_fc_weight: Vec, pub mlp_fc_bias: Vec, - /// MLP proj: [3072, 768] + bias [768] + /// MLP proj: [3072, 768] + bias \[768\] pub mlp_proj_weight: Vec, pub mlp_proj_bias: Vec, } diff --git a/src/hpc/holo.rs b/src/hpc/holo.rs index 60ea7d99..0c25c9df 100644 --- a/src/hpc/holo.rs +++ b/src/hpc/holo.rs @@ -72,7 +72,7 @@ pub fn phase_unbind_i8(bound: &[u8], key: &[u8]) -> Vec { /// Wasserstein-1 (Earth Mover's) distance between two PRE-SORTED u8 vectors. /// -/// For sorted vectors, Wasserstein-1 = Σ|a[i] - b[i]|. +/// For sorted vectors, Wasserstein-1 = Σ|a\[i\] - b\[i\]|. /// Same cost as Hamming distance, but gives a TRUE metric spatial distance. /// /// IMPORTANT: Both inputs MUST be sorted ascending. @@ -756,9 +756,9 @@ const CONTAINER_BYTES: usize = 2048; /// Each carrier is stored as i8 (signed, range -128..+127) because waveforms /// oscillate around zero. pub struct CarrierBasis { - /// Cosine carriers: basis_cos[freq_idx][sample_idx] → i8 + /// Cosine carriers: `basis_cos[freq_idx][sample_idx]` → i8 pub basis_cos: [[i8; 2048]; 16], - /// Sine carriers: basis_sin[freq_idx][sample_idx] → i8 + /// Sine carriers: `basis_sin[freq_idx][sample_idx]` → i8 pub basis_sin: [[i8; 2048]; 16], } @@ -832,7 +832,7 @@ impl CarrierBasis { /// Encode a concept as a carrier at a specific frequency with given phase and amplitude. /// /// Adds to the existing waveform (accumulation, not replacement): -/// container[j] += cos(φ)·basis_cos[f][j] - sin(φ)·basis_sin[f][j] +/// `container[j] += cos(φ)·basis_cos[f][j] - sin(φ)·basis_sin[f][j]` /// (scaled by amplitude / CARRIER_AMPLITUDE) /// /// Uses float per element for phase precision. Maps to VCVTDQ2PS + VMULPS + @@ -863,8 +863,8 @@ pub fn carrier_encode(container: &mut [i8], basis: &CarrierBasis, freq_idx: u8, /// Decode the amplitude and phase of a specific frequency from the waveform. /// /// Demodulation: dot product of waveform with cos and sin carriers, then atan2. -/// cos_component = Σ container[j] · basis_cos[f][j] -/// sin_component = Σ container[j] · basis_sin[f][j] +/// `cos_component = Σ container[j] · basis_cos[f][j]` +/// `sin_component = Σ container[j] · basis_sin[f][j]` /// phase = atan2(sin_component, cos_component) /// amplitude = sqrt(cos² + sin²) / N /// @@ -2010,7 +2010,7 @@ pub fn focus_l1(a: &[u8], b: &[u8], mask_x: u8, mask_y: u8, mask_z: u32) -> (u64 // ============================================================================ /// Expand the 48-bit focus address into a full 2048-byte mask. -/// out[i] = 0xFF if position i is in focus, 0x00 otherwise. +/// out\[i\] = 0xFF if position i is in focus, 0x00 otherwise. pub fn materialize_focus_mask(mask_x: u8, mask_y: u8, mask_z: u32) -> [u8; 2048] { let mut mask = [0u8; 2048]; diff --git a/src/hpc/jina/runtime.rs b/src/hpc/jina/runtime.rs index 398d2930..aababaa5 100644 --- a/src/hpc/jina/runtime.rs +++ b/src/hpc/jina/runtime.rs @@ -134,7 +134,7 @@ pub struct ModelRuntime { pub tokens: Vec, /// 256-entry palette with precomputed 256×256 distance table. pub palette: JinaPalette, - /// SimilarityTable: 256-entry CDF calibration (distance → f32 [0,1]). + /// SimilarityTable: 256-entry CDF calibration (distance → f32 \[0,1\]). pub similarity: [f32; 256], } diff --git a/src/hpc/jitson/mod.rs b/src/hpc/jitson/mod.rs index 2393d46c..13f4e721 100644 --- a/src/hpc/jitson/mod.rs +++ b/src/hpc/jitson/mod.rs @@ -9,7 +9,7 @@ //! - [`packed`]: Re-export of [`crate::hpc::packed`] (PackedDatabase) //! //! ## `jit-native` feature (Cranelift JIT compilation) -//! See [`crate::hpc::jitson_cranelift`] for: +//! See `crate::hpc::jitson_cranelift` (feature `jit-native`) for: //! - `ScanParams`, `PhilosopherIR`, `RecipeIR`, `JitError` //! - `CpuCaps` — CPU feature detection //! - `JitEngine`, `JitEngineBuilder` — compile scan params to native code diff --git a/src/hpc/linalg/svd.rs b/src/hpc/linalg/svd.rs index 6307bcf7..8cc6dd80 100644 --- a/src/hpc/linalg/svd.rs +++ b/src/hpc/linalg/svd.rs @@ -383,7 +383,7 @@ fn golub_reinsch(a: &[[f32; N]; M]) -> Svd /// Build the essential Householder vector for vector `x`. /// /// Returns `(v, sigma)` where: -/// - `v` is the reflector vector (same length as `x`, normalized so v[0]=1) +/// - `v` is the reflector vector (same length as `x`, normalized so v\[0\]=1) /// - `sigma` = the first element after reflection (i.e. H·x = [sigma,0,…,0]ᵀ) /// /// The reflector is H = I − tau·v·vᵀ with tau = 2/‖v‖². diff --git a/src/hpc/merkle_tree.rs b/src/hpc/merkle_tree.rs index d9f848f9..4bb3d26d 100644 --- a/src/hpc/merkle_tree.rs +++ b/src/hpc/merkle_tree.rs @@ -65,8 +65,8 @@ pub struct MerkleTree { pub root: MerkleRoot, /// Level 1: branch hashes (8 x 48 bits = 384 bits). /// - /// Indices: [0] identity, [1] nars, [2] edges, [3] rl, - /// [4] bloom, [5] qualia, [6] adjacency, [7] content. + /// Indices: \[0\] identity, \[1\] nars, \[2\] edges, \[3\] rl, + /// \[4\] bloom, \[5\] qualia, \[6\] adjacency, \[7\] content. pub branches: [MerkleRoot; NUM_BRANCHES], /// Level 2: leaf hashes (64 x 48 bits = 3072 bits). pub leaves: [MerkleRoot; NUM_LEAVES], diff --git a/src/hpc/models/safetensors.rs b/src/hpc/models/safetensors.rs index 8f9f70cc..f7fe79b4 100644 --- a/src/hpc/models/safetensors.rs +++ b/src/hpc/models/safetensors.rs @@ -59,7 +59,7 @@ impl SafeTensorsFile { }) } - /// Read a tensor as Vec (little-endian F32). + /// Read a tensor as `Vec` (little-endian F32). pub fn read_f32(&self, name: &str) -> Result, String> { let meta = self .tensors @@ -76,7 +76,7 @@ impl SafeTensorsFile { .collect()) } - /// Read a tensor as Vec stored as raw u16 (for F16 tensors). + /// Read a tensor as `Vec` stored as raw u16 (for F16 tensors). pub fn read_f16_raw(&self, name: &str) -> Result, String> { let meta = self .tensors diff --git a/src/hpc/openchat/weights.rs b/src/hpc/openchat/weights.rs index 7ada5622..ddc4e260 100644 --- a/src/hpc/openchat/weights.rs +++ b/src/hpc/openchat/weights.rs @@ -39,7 +39,7 @@ pub const GQA_RATIO: usize = NUM_Q_HEADS / NUM_KV_HEADS; // 4 /// Weights for one Mistral transformer layer. #[derive(Clone)] pub struct MistralLayerWeights { - /// Attention RMSNorm weight [4096] (no bias). + /// Attention RMSNorm weight \[4096\] (no bias). pub attn_norm: Vec, /// Q projection: [4096, 4096] → pre-transposed to [4096, 4096]. pub attn_q: Vec, @@ -49,7 +49,7 @@ pub struct MistralLayerWeights { pub attn_v: Vec, /// Output projection: [4096, 4096] → pre-transposed. pub attn_output: Vec, - /// FFN RMSNorm weight [4096]. + /// FFN RMSNorm weight \[4096\]. pub ffn_norm: Vec, /// Gate projection (SiLU): [14336, 4096] → pre-transposed. pub ffn_gate: Vec, @@ -66,7 +66,7 @@ pub struct OpenChatWeights { pub token_embd: Vec, /// Transformer layers. pub layers: Vec, - /// Final RMSNorm weight [4096]. + /// Final RMSNorm weight \[4096\]. pub output_norm: Vec, /// Output projection (lm_head): [32000, 4096]. /// May be tied to token_embd (same data). diff --git a/src/hpc/renderer.rs b/src/hpc/renderer.rs index 80da2fe9..9122e975 100644 --- a/src/hpc/renderer.rs +++ b/src/hpc/renderer.rs @@ -601,7 +601,7 @@ impl UpdatePriority { /// Classify each node by distance to viewport center. /// -/// Returns a Vec of length `len` (active nodes only). Trailing +/// Returns a `Vec` of length `len` (active nodes only). Trailing /// padded slots are not classified — they're never integrated regardless. pub fn classify_priorities(positions: &[f32], len: usize, vp: &Viewport) -> Vec { let mut out = Vec::with_capacity(len); diff --git a/src/hpc/safetensors.rs b/src/hpc/safetensors.rs index f9fb29c2..afd71d9b 100644 --- a/src/hpc/safetensors.rs +++ b/src/hpc/safetensors.rs @@ -242,7 +242,7 @@ fn extract_json_array_u64(obj: &str, key: &str) -> Option> { /// /// The returned `GgufFile` has: /// - `tensor_data_offset`: absolute byte offset where tensor data starts -/// - `tensors`: Vec with offsets relative to data start +/// - `tensors`: `Vec` with offsets relative to data start /// - `version`: 0 (not a GGUF version) /// - `alignment`: 1 (safetensors has no alignment padding) pub fn read_safetensors_header(reader: &mut R) -> Result { diff --git a/src/hpc/signature_pde.rs b/src/hpc/signature_pde.rs index 33910b4a..990746b0 100644 --- a/src/hpc/signature_pde.rs +++ b/src/hpc/signature_pde.rs @@ -32,7 +32,7 @@ //! three rolling row-indexed buffers (`prev2`, `prev1`, `cur`) instead of a //! full `n*m` grid, and — because the interior of one diagonal has no //! cross-cell dependency — each diagonal's interior is computed -//! [`LANES`]-wide via [`F64x8`]. +//! `LANES`-wide via [`F64x8`]. //! //! `y`'s increments are stored **reversed per dimension** (`dyr`): the //! diagonal walk needs `dy[j-1]` for `j` decreasing as row `i` increases, diff --git a/src/hpc/soa.rs b/src/hpc/soa.rs index 883b1476..614463a4 100644 --- a/src/hpc/soa.rs +++ b/src/hpc/soa.rs @@ -4,7 +4,7 @@ //! "struct-of-arrays" storage shape, plus scalar deinterleave / interleave //! free functions: //! -//! - [`soa_struct!`] macro — generates a named-field SoA struct from a +//! - [`soa_struct!`](crate::soa_struct) macro — generates a named-field SoA struct from a //! struct-like declaration. Use when field names matter to callers //! (e.g. `means_x`, `means_y`, `means_z` for a Gaussian batch). //! - [`SoaVec`] generic — `[Vec; N]` wrapper. Use when fields are diff --git a/src/hpc/surround_metadata.rs b/src/hpc/surround_metadata.rs index 9c702983..a7eb2d33 100644 --- a/src/hpc/surround_metadata.rs +++ b/src/hpc/surround_metadata.rs @@ -173,7 +173,7 @@ impl SurroundBundler { /// Convert a Fingerprint<256> (16Kbit) to an f64 vector of length D (8192). /// Each pair of bits maps to one bipolar f64 dimension: -/// bits[2k], bits[2k+1] → value ∈ {-1, -0.33, 0.33, 1} +/// bits\[2k\], bits[2k+1] → value ∈ {-1, -0.33, 0.33, 1} pub fn fingerprint_to_f64(fp: &Fingerprint<256>) -> Vec { let mut out = vec![0.0f64; D]; let bytes = fp.as_bytes(); diff --git a/src/hpc/vnni_gemm.rs b/src/hpc/vnni_gemm.rs index 05c08212..8a2f8d4d 100644 --- a/src/hpc/vnni_gemm.rs +++ b/src/hpc/vnni_gemm.rs @@ -2,7 +2,7 @@ //! //! Uses `VPDPBUSD` (AVX-512 VNNI) to compute 4-element u8*i8 dot products //! in a single instruction, accumulating into i32. Falls back to the scalar -//! [`int8_gemm_i32`](super::quantized::int8_gemm_i32) on hardware without +//! [`int8_gemm_i32`] on hardware without //! VNNI support. //! //! # VNNI dot semantics diff --git a/src/palette_codec.rs b/src/palette_codec.rs index b1e39d85..d334db52 100644 --- a/src/palette_codec.rs +++ b/src/palette_codec.rs @@ -134,7 +134,7 @@ pub fn compression_ratio(bits_per_index: usize) -> f32 { /// Transcode: change bit width without full decode/re-encode. /// /// Useful when a palette grows (e.g., 4-bit → 5-bit after inserting a 17th entry). -/// More efficient than unpack→repack because it avoids the intermediate Vec. +/// More efficient than unpack→repack because it avoids the intermediate `Vec`. pub fn transcode(packed: &[u64], old_bits: usize, new_bits: usize, count: usize) -> Vec { assert!(old_bits > 0 && old_bits <= 8); assert!(new_bits > 0 && new_bits <= 8); diff --git a/src/simd.rs b/src/simd.rs index 0904c2ab..b347724f 100644 --- a/src/simd.rs +++ b/src/simd.rs @@ -1,4 +1,4 @@ -//! SIMD polyfill — `crate::simd::F32x16` dispatches via LazyLock. +//! SIMD polyfill — `crate::simd::F32x16` dispatches via `LazyLock`. //! //! Same pattern as `backend/native.rs`: detect once, dispatch forever. //! AVX-512 → AVX2 → Scalar. Consumer writes `crate::simd::F32x16`. Period. @@ -192,7 +192,7 @@ pub const PREFERRED_U64_LANES: usize = 2; // WASM SIMD128: i64x2 = 2 × u64 #[cfg(not(any(target_arch = "x86_64", target_arch = "aarch64", target_arch = "wasm32")))] pub const PREFERRED_U64_LANES: usize = 4; -/// Preferred i16 SIMD width (for Base17 L1 on i16[17]). +/// Preferred i16 SIMD width (for Base17 L1 on i16\[17\]). /// AVX-512: 32 lanes (__m512i via epi16). AVX2: 16 lanes (__m256i). /// NEON: 8 lanes (int16x8_t). Base17 has 17 dims — NEON needs 3 loads /// (8+8+1), A72 dual pipeline hides latency on the third. diff --git a/src/simd_amx.rs b/src/simd_amx.rs index 1dca8829..72fd90b4 100644 --- a/src/simd_amx.rs +++ b/src/simd_amx.rs @@ -133,7 +133,7 @@ static AMX_AVAILABLE: std::sync::LazyLock = std::sync::LazyLock::new(detec static AMX_TILE_AVAILABLE: std::sync::LazyLock = std::sync::LazyLock::new(detect_amx_tile); /// AMX-TILE present, OS-enabled, and permitted for this process — the gate -/// for tile-state ops of ANY tier. See [`AMX_TILE_AVAILABLE`]; [`amx_available`] +/// for tile-state ops of ANY tier. See `AMX_TILE_AVAILABLE`; [`amx_available`] /// is this plus the AMX-INT8 silicon bit. /// /// # Examples @@ -315,7 +315,7 @@ pub fn amx_report() -> String { /// VNNI u8×i8 dot product: 64 multiply-accumulates per instruction. /// -/// Computes: for each 32-bit lane, sum of 4 products: u8[k] × i8[k]. +/// Computes: for each 32-bit lane, sum of 4 products: u8\[k\] × i8\[k\]. /// 16 lanes × 4 products = 64 MACs total. /// /// Used by ThinkingEngine for the u8 distance table × i8 energy MatVec. diff --git a/src/simd_avx2.rs b/src/simd_avx2.rs index 19622d4e..54b6dc24 100644 --- a/src/simd_avx2.rs +++ b/src/simd_avx2.rs @@ -1436,7 +1436,7 @@ impl I16x32 { // ── U8x64 byte-level operations (scalar fallback for AVX2 tier) ────────── // These match the AVX-512 U8x64 methods in simd_avx512.rs. impl U8x64 { - /// Byte-wise equality mask: bit i set if self[i] == other[i]. + /// Byte-wise equality mask: bit i set if self\[i\] == other\[i\]. /// /// Composed from two native AVX2 `U8x32::cmpeq_mask` calls (lanes /// 0..32 in the low half, 32..64 in the high half) instead of a @@ -1484,7 +1484,7 @@ impl U8x64 { } Self(out) } - /// Byte-wise UNSIGNED greater-than mask: bit i set if self[i] > other[i]. + /// Byte-wise UNSIGNED greater-than mask: bit i set if self\[i\] > other\[i\]. /// /// Composed from two native AVX2 `U8x32::cmpgt_mask` calls, which /// already carry the sign-bias XOR trick AVX2 needs to get an unsigned diff --git a/src/simd_avx512.rs b/src/simd_avx512.rs index 31f3b3ef..9af9aa1a 100644 --- a/src/simd_avx512.rs +++ b/src/simd_avx512.rs @@ -604,7 +604,7 @@ impl U8x64 { // Reference: Pumpkin/Minecraft-derived modules (palette_codec.rs, // nibble.rs, byte_scan.rs) use these for 4-bit packing and scanning. - /// Byte-wise equality comparison. Returns 64-bit mask: bit i set if a[i] == b[i]. + /// Byte-wise equality comparison. Returns 64-bit mask: bit i set if a\[i\] == b\[i\]. #[inline(always)] pub fn cmpeq_mask(self, other: Self) -> u64 { unsafe { _mm512_cmpeq_epi8_mask(self.0, other.0) } @@ -639,7 +639,7 @@ impl U8x64 { // ── Tier 1: seismon rasterizer primitives ───────────────────────── - /// Pairwise unsigned byte average: (a[i] + b[i] + 1) >> 1 per byte. + /// Pairwise unsigned byte average: (a\[i\] + b\[i\] + 1) >> 1 per byte. /// Core op for 4×4 mipmap downsample (vpavgb + horizontal pair = 2 ops). #[inline(always)] pub fn pairwise_avg(self, other: Self) -> Self { @@ -648,7 +648,7 @@ impl U8x64 { } /// Byte-wise unsigned greater-than comparison. Returns 64-bit mask: - /// bit i set if self[i] > other[i]. Symmetric to `cmpeq_mask`. + /// bit i set if self\[i\] > other\[i\]. Symmetric to `cmpeq_mask`. /// Used for threshold density fields, depth/Z-test, hit-tests. #[inline(always)] pub fn cmpgt_mask(self, other: Self) -> u64 { @@ -2057,7 +2057,7 @@ impl I8x64 { Self(unsafe { _mm512_max_epi8(self.0, other.0) }) } - /// Compare-greater-than: returns 64-bit mask. Bit i set where self[i] > other[i]. + /// Compare-greater-than: returns 64-bit mask. Bit i set where self\[i\] > other\[i\]. #[inline(always)] pub fn cmp_gt(self, other: Self) -> u64 { unsafe { _mm512_cmpgt_epi8_mask(self.0, other.0) } @@ -2152,7 +2152,7 @@ impl I8x32 { #[cfg(not(all(target_feature = "avx", not(target_feature = "avx2"))))] /// Compare-greater-than: returns 32-bit mask via packed-byte movemask. - /// Bit i set where self[i] > other[i]. + /// Bit i set where self\[i\] > other\[i\]. #[inline(always)] pub fn cmp_gt(self, other: Self) -> u32 { unsafe { _mm256_movemask_epi8(_mm256_cmpgt_epi8(self.0, other.0)) as u32 } @@ -2266,7 +2266,7 @@ impl I16x32 { Self(unsafe { _mm512_max_epi16(self.0, other.0) }) } - /// Compare-greater-than: returns 32-bit mask. Bit i set where self[i] > other[i]. + /// Compare-greater-than: returns 32-bit mask. Bit i set where self\[i\] > other\[i\]. #[inline(always)] pub fn cmp_gt(self, other: Self) -> u32 { unsafe { _mm512_cmpgt_epi16_mask(self.0, other.0) } @@ -2361,7 +2361,7 @@ impl I16x16 { #[cfg(not(all(target_feature = "avx", not(target_feature = "avx2"))))] /// Compare-greater-than: returns 16-bit mask via packed-word movemask. - /// Bit i set where self[i] > other[i]. + /// Bit i set where self\[i\] > other\[i\]. #[inline(always)] pub fn cmp_gt(self, other: Self) -> u16 { unsafe { diff --git a/src/simd_int_ops.rs b/src/simd_int_ops.rs index 24c104b8..411f71be 100644 --- a/src/simd_int_ops.rs +++ b/src/simd_int_ops.rs @@ -237,7 +237,7 @@ pub fn dot_i16(a: &[i16], b: &[i16]) -> i64 { /// | `avx512vnni` | `VPDPBUSD` zmm — 16 i32 lanes (CLX → Zen 4 / SPR) | /// | `avxvnni` | `VPDPBUSD` ymm — 8 i32 lanes (Alder/Arrow Lake, Zen 4)| /// | `neon,dotprod` *(planned)* | NEON `SDOT` (A76+ / Apple M-series) | -/// | *(none)* | Scalar reference [`hpc::quantized::int8_gemm_i32`] | +/// | *(none)* | Scalar reference [`crate::hpc::quantized::int8_gemm_i32`] | /// /// Arm precedence is widest-vector-first: when several `target_feature` /// flags are set simultaneously (e.g. Sapphire Rapids enables `avx512vnni` diff --git a/src/simd_masking_ops.rs b/src/simd_masking_ops.rs index eb390272..fc3dff9c 100644 --- a/src/simd_masking_ops.rs +++ b/src/simd_masking_ops.rs @@ -1751,7 +1751,7 @@ fn group_walk( } /// Keyed group-count: for every row `i` selected by `mask_words` (`i < -/// keys.len()`), adds 1 into `out[keys[i]]` — provided `keys[i] < +/// keys.len()`), adds 1 into `out[keys\[i\]]` — provided `keys\[i\] < /// out.len()`. `COUNT(*) … GROUP BY key` in one pass, replacing K masked /// popcounts (one per group). /// @@ -3529,7 +3529,7 @@ pub fn ne_u32_to_mask(values: &[u32], needle: u32, out_words: &mut [u64]) { /// (unlike the u32/i32 families' 16-lane groups, four of which pack into one /// word). The final partial group is zero-padded into one register and run /// through the same packed compare, with the padding lanes' bits masked off -/// by [`word_range_mask`] — no scalar tail, so the tail cannot disagree with +/// by `word_range_mask` — no scalar tail, so the tail cannot disagree with /// the body. /// /// # Panics @@ -3574,7 +3574,7 @@ pub fn eq_u8_to_mask(values: &[u8], needle: u8, out_words: &mut [u64]) { /// Runs 64 lanes at a time through [`crate::simd::U8x64::cmpgt_mask`] — one /// whole output word per chunk. The final partial group is zero-padded into /// one register and run through the same packed compare, with the padding -/// lanes' bits masked off by [`word_range_mask`]. +/// lanes' bits masked off by `word_range_mask`. /// /// # Panics /// @@ -4022,7 +4022,7 @@ pub fn mask_not_assign(dst: &mut [u64], n_rows: usize) { /// The write is at most three passes over `out_words`: every word strictly /// before `lo`'s word is zeroed, every word strictly after `hi`'s last live /// word is zeroed, whole interior words are written `u64::MAX`, and the (at -/// most two) edge words each get one computed mask ([`word_range_mask`]). +/// most two) edge words each get one computed mask (`word_range_mask`). /// When `lo` and `hi` fall in the SAME word, that word is written exactly /// once through the single-word branch — never as two overlapping edge /// writes. @@ -4770,7 +4770,7 @@ pub fn lt_i32_to_mask_under(values: &[i32], threshold: i32, under: &[u64], out_w /// Packs `values[i] >= threshold` (signed) AND `under`, complementing /// [`lt_i32_to_mask_under`]'s per-group bits *inside* the group so the tail -/// law stays [`live16`]'s to enforce, never a whole-word complement. Same +/// law stays `live16`'s to enforce, never a whole-word complement. Same /// contract as [`gt_i32_to_mask_under`]; gated form of [`ge_i32_to_mask`]. /// /// # Panics diff --git a/src/simd_neon.rs b/src/simd_neon.rs index c0b7ed30..1fb0aa50 100644 --- a/src/simd_neon.rs +++ b/src/simd_neon.rs @@ -83,7 +83,7 @@ pub unsafe fn hamming_u8x16(a: &[u8; 16], b: &[u8; 16]) -> u32 { vgetq_lane_u64(sum64, 0) as u32 + vgetq_lane_u64(sum64, 1) as u32 } -/// Base17 L1 distance: |a[i] - b[i]| summed over 17 i16 elements. +/// Base17 L1 distance: |a\[i\] - b\[i\]| summed over 17 i16 elements. /// Processes 8 elements per NEON instruction (int16x8_t), tail scalar. #[cfg(target_arch = "aarch64")] #[inline(always)] @@ -1353,7 +1353,7 @@ impl I8x16 { Self(unsafe { vmaxq_s8(self.0, other.0) }) } - /// Compare-greater-than: returns 16-bit mask. Bit i set where self[i] > other[i]. + /// Compare-greater-than: returns 16-bit mask. Bit i set where self\[i\] > other\[i\]. /// /// Register-level compare: it takes a second register, so it is binary in form. /// The masking-ops predicates call register compares like this one with a @@ -1455,7 +1455,7 @@ impl I16x8 { Self(unsafe { vmaxq_s16(self.0, other.0) }) } - /// Compare-greater-than: returns 8-bit mask. Bit i set where self[i] > other[i]. + /// Compare-greater-than: returns 8-bit mask. Bit i set where self\[i\] > other\[i\]. /// /// Register-level compare: it takes a second register, so it is binary in form. /// The masking-ops predicates call register compares like this one with a diff --git a/src/simd_nightly/_original_draft.rs b/src/simd_nightly/_original_draft.rs index 9b5af799..f381eb79 100644 --- a/src/simd_nightly/_original_draft.rs +++ b/src/simd_nightly/_original_draft.rs @@ -252,7 +252,7 @@ impl F32Mask16 { self.0.to_bitmask() as u16 } - /// Per-lane select: returns `true_val[i]` where mask[i] is set, + /// Per-lane select: returns `true_val[i]` where mask\[i\] is set, /// else `false_val[i]`. #[inline(always)] pub fn select(self, true_val: F32x16, false_val: F32x16) -> F32x16 { diff --git a/src/simd_nightly/masks.rs b/src/simd_nightly/masks.rs index 03b76be9..ab9b7f7d 100644 --- a/src/simd_nightly/masks.rs +++ b/src/simd_nightly/masks.rs @@ -31,7 +31,7 @@ impl F32Mask16 { Self(Mask::::from_bitmask(bits as u64)) } - /// Per-lane select: returns `true_val[i]` where mask[i] is set, + /// Per-lane select: returns `true_val[i]` where mask\[i\] is set, /// else `false_val[i]`. #[inline(always)] pub fn select(self, true_val: F32x16, false_val: F32x16) -> F32x16 { @@ -73,7 +73,7 @@ impl F32Mask8 { Self(Mask::::from_bitmask(bits as u64)) } - /// Per-lane select: returns `true_val[i]` where mask[i] is set, + /// Per-lane select: returns `true_val[i]` where mask\[i\] is set, /// else `false_val[i]`. #[inline(always)] pub fn select(self, true_val: F32x8, false_val: F32x8) -> F32x8 { @@ -118,7 +118,7 @@ impl F64Mask8 { Self(Mask::::from_bitmask(bits as u64)) } - /// Per-lane select: returns `true_val[i]` where mask[i] is set, + /// Per-lane select: returns `true_val[i]` where mask\[i\] is set, /// else `false_val[i]`. #[inline(always)] pub fn select(self, true_val: F64x8, false_val: F64x8) -> F64x8 { @@ -160,7 +160,7 @@ impl F64Mask4 { Self(Mask::::from_bitmask(bits as u64)) } - /// Per-lane select: returns `true_val[i]` where mask[i] is set, + /// Per-lane select: returns `true_val[i]` where mask\[i\] is set, /// else `false_val[i]`. #[inline(always)] pub fn select(self, true_val: F64x4, false_val: F64x4) -> F64x4 { diff --git a/src/simd_wasm.rs b/src/simd_wasm.rs index 6f3622b8..b0a2e0ca 100644 --- a/src/simd_wasm.rs +++ b/src/simd_wasm.rs @@ -843,7 +843,7 @@ pub mod wasm32_simd { Self(v128_bitselect(self.0, other.0, i8x16_gt(self.0, other.0))) } - /// Compare-greater-than: returns a 16-bit mask. Bit i set where self[i] > other[i]. + /// Compare-greater-than: returns a 16-bit mask. Bit i set where self\[i\] > other\[i\]. /// /// Register-level compare: it takes a second register, so it is binary in form. /// The masking-ops predicates call register compares like this one with a From 5f60c106254b3ad0ddb10365b7863051eac52384 Mon Sep 17 00:00:00 2001 From: Claude Date: Sat, 10 Oct 2026 09:21:06 +0000 Subject: [PATCH 3/3] ci(cargo-careful): install rust-src with the nightly toolchain careful rebuilds std from source and needs rust-src; without it a local run stalled for 25 minutes with no compiler process. With it, the cpu_guard smoke run passes (8/8). Co-Authored-By: Claude Opus 5.5 Claude-Session: https://claude.ai/code/session_011BMJnDBAfzcuQh5HeT39Rh --- .github/workflows/ci.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/ci.yaml b/.github/workflows/ci.yaml index c7837fc2..2e2476c9 100644 --- a/.github/workflows/ci.yaml +++ b/.github/workflows/ci.yaml @@ -420,6 +420,10 @@ jobs: steps: - uses: actions/checkout@v4 - uses: dtolnay/rust-toolchain@nightly + with: + # careful rebuilds std from source; without rust-src it stalls + # (seen locally: no compiler process, no output, for 25 min). + components: rust-src - uses: Swatinem/rust-cache@v2 - uses: taiki-e/install-action@nextest - name: Install cargo-careful