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Merge tag 'edac_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras
Pull EDAC updates from Borislav Petkov: - Add support for new AMD family 0x1a models to amd64_edac - Add an EDAC driver for the AMD VersalNET memory controller which reports hw errors from different IP blocks in the fabric using an IPC-type transport - Drop the silly static number of memory controllers in the Intel EDAC drivers (skx, i10nm) in favor of a flexible array so that former doesn't need to be increased with every new generation which adds more memory controllers; along with a proper refactoring - Add support for two Alder Lake-S SOCs to ie31200_edac - Add an EDAC driver for ADM Cortex A72 cores, and specifically for reporting L1 and L2 cache errors - Last but not least, the usual fixes, cleanups and improvements all over the subsystem * tag 'edac_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: (23 commits) EDAC/versalnet: Return the correct error in mc_probe() EDAC/mc_sysfs: Increase legacy channel support to 16 EDAC/amd64: Add support for AMD family 1Ah-based newer models EDAC: Add a driver for the AMD Versal NET DDR controller dt-bindings: memory-controllers: Add support for Versal NET EDAC RAS: Export log_non_standard_event() to drivers cdx: Export Symbols for MCDI RPC and Initialization cdx: Split mcdi.h and reorganize headers EDAC/skx_common: Use topology_physical_package_id() instead of open coding EDAC: Fix wrong executable file modes for C source files EDAC/altera: Use dev_fwnode() EDAC/skx_common: Remove unused *NUM*_IMC macros EDAC/i10nm: Reallocate skx_dev list if preconfigured cnt != runtime cnt EDAC/skx_common: Remove redundant upper bound check for res->imc EDAC/skx_common: Make skx_dev->imc[] a flexible array EDAC/skx_common: Swap memory controller index mapping EDAC/skx_common: Move mc_mapping to be a field inside struct skx_imc EDAC/{skx_common,skx}: Use configuration data, not global macros EDAC/i10nm: Skip DIMM enumeration on a disabled memory controller EDAC/ie31200: Add two more Intel Alder Lake-S SoCs for EDAC support ...
2 parents 88b4893 + 69ed025 commit 03f76dd

29 files changed

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‎Documentation/devicetree/bindings/arm/cpus.yaml‎

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@@ -353,6 +353,12 @@ properties:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Link to Mediatek Cache Coherent Interconnect
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edac-enabled:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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A72 CPUs support Error Detection And Correction (EDAC) on their L1 and
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L2 caches. This flag marks this function as usable.
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qcom,saw:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
@@ -399,6 +405,17 @@ properties:
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allOf:
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- $ref: /schemas/cpu.yaml#
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- $ref: /schemas/opp/opp-v1.yaml#
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- if:
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not:
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properties:
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compatible:
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contains:
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const: arm,cortex-a72
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then:
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# Allow edac-enabled only for Cortex A72
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properties:
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edac-enabled: false
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- if:
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# If the enable-method property contains one of those values
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properties:

‎Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal NET Memory Controller
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maintainers:
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- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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description:
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The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
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compact and extended memory interfaces. Versal NET DDR memory controller
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has an optional ECC support which correct single bit ECC errors and detect
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double bit ECC errors. It also has support for reporting other errors like
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MMCM (Mixed-Mode Clock Manager) errors and General software errors.
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properties:
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compatible:
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const: xlnx,versal-net-ddrmc5
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amd,rproc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to the remoteproc_r5 rproc node using which APU interacts
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with remote processor. APU primarily communicates with the RPU for
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accessing the DDRMC address space and getting error notification.
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required:
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- compatible
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- amd,rproc
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additionalProperties: false
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examples:
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- |
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memory-controller {
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compatible = "xlnx,versal-net-ddrmc5";
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amd,rproc = <&remoteproc_r5>;
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};

‎MAINTAINERS‎

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@@ -8745,16 +8745,20 @@ F: drivers/edac/thunderx_edac*
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EDAC-CORE
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M: Borislav Petkov <bp@alien8.de>
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M: Tony Luck <tony.luck@intel.com>
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R: James Morse <james.morse@arm.com>
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R: Mauro Carvalho Chehab <mchehab@kernel.org>
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R: Robert Richter <rric@kernel.org>
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L: linux-edac@vger.kernel.org
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S: Supported
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac-for-next
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F: Documentation/driver-api/edac.rst
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F: drivers/edac/
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F: include/linux/edac.h
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EDAC-A72
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M: Vijay Balakrishna <vijayb@linux.microsoft.com>
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M: Tyler Hicks <code@tyhicks.com>
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L: linux-edac@vger.kernel.org
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S: Supported
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F: drivers/edac/a72_edac.c
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EDAC-DMC520
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M: Lei Wang <lewan@microsoft.com>
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L: linux-edac@vger.kernel.org
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F: Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml
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F: drivers/edac/versal_edac.c
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XILINX VERSALNET EDAC DRIVER
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M: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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S: Maintained
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F: Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml
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F: drivers/edac/versalnet_edac.c
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F: include/linux/cdx/edac_cdx_pcol.h
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XILINX WATCHDOG DRIVER
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M: Srinivas Neeli <srinivas.neeli@amd.com>
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R: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

‎drivers/cdx/controller/cdx_controller.c‎

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#include "cdx_controller.h"
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#include "../cdx.h"
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#include "mcdi_functions.h"
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#include "mcdi.h"
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#include "mcdid.h"
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static unsigned int cdx_mcdi_rpc_timeout(struct cdx_mcdi *cdx, unsigned int cmd)
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{

‎drivers/cdx/controller/cdx_rpmsg.c‎

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#include "../cdx.h"
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#include "cdx_controller.h"
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#include "mcdi_functions.h"
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#include "mcdi.h"
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#include "mcdid.h"
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static struct rpmsg_device_id cdx_rpmsg_id_table[] = {
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{ .name = "mcdi_ipc" },

‎drivers/cdx/controller/mcdi.c‎

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#include <linux/log2.h>
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#include <linux/net_tstamp.h>
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#include <linux/wait.h>
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#include <linux/cdx/bitfield.h>
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#include "bitfield.h"
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#include "mcdi.h"
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#include <linux/cdx/mcdi.h>
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#include "mcdid.h"
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static void cdx_mcdi_cancel_cmd(struct cdx_mcdi *cdx, struct cdx_mcdi_cmd *cmd);
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static void cdx_mcdi_wait_for_cleanup(struct cdx_mcdi *cdx);
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return cdx->mcdi_ops->mcdi_rpc_timeout(cdx, cmd);
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}
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/**
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* cdx_mcdi_init - Initialize MCDI (Management Controller Driver Interface) state
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* @cdx: Handle to the CDX MCDI structure
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*
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* This function allocates and initializes internal MCDI structures and resources
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* for the CDX device, including the workqueue, locking primitives, and command
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* tracking mechanisms. It sets the initial operating mode and prepares the device
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* for MCDI operations.
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*
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* Return:
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* * 0 - on success
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* * -ENOMEM - if memory allocation or workqueue creation fails
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*/
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int cdx_mcdi_init(struct cdx_mcdi *cdx)
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{
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struct cdx_mcdi_iface *mcdi;
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fail:
129143
return rc;
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}
145+
EXPORT_SYMBOL_GPL(cdx_mcdi_init);
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/**
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* cdx_mcdi_finish - Cleanup MCDI (Management Controller Driver Interface) state
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* @cdx: Handle to the CDX MCDI structure
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*
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* This function is responsible for cleaning up the MCDI (Management Controller Driver Interface)
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* resources associated with a cdx_mcdi structure. Also destroys the mcdi workqueue.
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*
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*/
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void cdx_mcdi_finish(struct cdx_mcdi *cdx)
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{
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struct cdx_mcdi_iface *mcdi;
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kfree(cdx->mcdi);
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cdx->mcdi = NULL;
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}
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EXPORT_SYMBOL_GPL(cdx_mcdi_finish);
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static bool cdx_mcdi_flushed(struct cdx_mcdi_iface *mcdi, bool ignore_cleanups)
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{
@@ -553,6 +577,19 @@ static void cdx_mcdi_start_or_queue(struct cdx_mcdi_iface *mcdi,
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cdx_mcdi_cmd_start_or_queue(mcdi, cmd);
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}
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/**
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* cdx_mcdi_process_cmd - Process an incoming MCDI response
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* @cdx: Handle to the CDX MCDI structure
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* @outbuf: Pointer to the response buffer received from the management controller
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* @len: Length of the response buffer in bytes
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*
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* This function handles a response from the management controller. It locates the
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* corresponding command using the sequence number embedded in the header,
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* completes the command if it is still pending, and initiates any necessary cleanup.
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*
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* The function assumes that the response buffer is well-formed and at least one
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* dword in size.
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*/
556593
void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct cdx_dword *outbuf, int len)
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{
558595
struct cdx_mcdi_iface *mcdi;
@@ -590,6 +627,7 @@ void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct cdx_dword *outbuf, int le
590627

591628
cdx_mcdi_process_cleanup_list(mcdi->cdx, &cleanup_list);
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}
630+
EXPORT_SYMBOL_GPL(cdx_mcdi_process_cmd);
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594632
static void cdx_mcdi_cmd_work(struct work_struct *context)
595633
{
@@ -757,6 +795,7 @@ int cdx_mcdi_rpc(struct cdx_mcdi *cdx, unsigned int cmd,
757795
return cdx_mcdi_rpc_sync(cdx, cmd, inbuf, inlen, outbuf, outlen,
758796
outlen_actual, false);
759797
}
798+
EXPORT_SYMBOL_GPL(cdx_mcdi_rpc);
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/**
762801
* cdx_mcdi_rpc_async - Schedule an MCDI command to run asynchronously

‎drivers/cdx/controller/mcdi_functions.c‎

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#include <linux/module.h>
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8-
#include "mcdi.h"
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#include "mcdi_functions.h"
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int cdx_mcdi_get_num_buses(struct cdx_mcdi *cdx)

‎drivers/cdx/controller/mcdi_functions.h‎

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#ifndef CDX_MCDI_FUNCTIONS_H
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#define CDX_MCDI_FUNCTIONS_H
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#include "mcdi.h"
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#include <linux/cdx/mcdi.h>
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#include "mcdid.h"
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#include "../cdx.h"
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/**

‎drivers/cdx/controller/mcdid.h‎

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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2008-2013 Solarflare Communications Inc.
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* Copyright (C) 2022-2025, Advanced Micro Devices, Inc.
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*/
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#ifndef CDX_MCDID_H
8+
#define CDX_MCDID_H
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#include <linux/mutex.h>
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#include <linux/kref.h>
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#include <linux/rpmsg.h>
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#include "mc_cdx_pcol.h"
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#ifdef DEBUG
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#define CDX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
18+
#define CDX_WARN_ON_PARANOID(x) WARN_ON(x)
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#else
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#define CDX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
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#define CDX_WARN_ON_PARANOID(x) do {} while (0)
22+
#endif
23+
24+
#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
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26+
static inline struct cdx_mcdi_iface *cdx_mcdi_if(struct cdx_mcdi *cdx)
27+
{
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return cdx->mcdi ? &cdx->mcdi->iface : NULL;
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}
30+
31+
int cdx_mcdi_rpc_async(struct cdx_mcdi *cdx, unsigned int cmd,
32+
const struct cdx_dword *inbuf, size_t inlen,
33+
cdx_mcdi_async_completer *complete,
34+
unsigned long cookie);
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int cdx_mcdi_wait_for_quiescence(struct cdx_mcdi *cdx,
36+
unsigned int timeout_jiffies);
37+
38+
/*
39+
* We expect that 16- and 32-bit fields in MCDI requests and responses
40+
* are appropriately aligned, but 64-bit fields are only
41+
* 32-bit-aligned.
42+
*/
43+
#define MCDI_BYTE(_buf, _field) \
44+
((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 1), \
45+
*MCDI_PTR(_buf, _field))
46+
#define MCDI_WORD(_buf, _field) \
47+
((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 2), \
48+
le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field)))
49+
#define MCDI_POPULATE_DWORD_1(_buf, _field, _name1, _value1) \
50+
CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), \
51+
MC_CMD_ ## _name1, _value1)
52+
#define MCDI_SET_QWORD(_buf, _field, _value) \
53+
do { \
54+
CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[0], \
55+
CDX_DWORD, (u32)(_value)); \
56+
CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[1], \
57+
CDX_DWORD, (u64)(_value) >> 32); \
58+
} while (0)
59+
#define MCDI_QWORD(_buf, _field) \
60+
(CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[0], CDX_DWORD) | \
61+
(u64)CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[1], CDX_DWORD) << 32)
62+
63+
#endif /* CDX_MCDID_H */

‎drivers/edac/Kconfig‎

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@@ -576,4 +576,20 @@ config EDAC_LOONGSON
576576
errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
577577
are compatible.
578578

579+
config EDAC_CORTEX_A72
580+
tristate "ARM Cortex A72"
581+
depends on ARM64
582+
help
583+
Support for L1/L2 cache error detection for ARM Cortex A72 processor.
584+
The detected and reported errors are from reading CPU/L2 memory error
585+
syndrome registers.
586+
587+
config EDAC_VERSALNET
588+
tristate "AMD VersalNET DDR Controller"
589+
depends on CDX_CONTROLLER && ARCH_ZYNQMP
590+
help
591+
Support for single bit error correction, double bit error detection
592+
and other system errors from various IP subsystems like RPU, NOCs,
593+
HNICX, PL on the AMD Versal NET DDR memory controller.
594+
579595
endif # EDAC

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