Skip to content

Commit 05fcd78

Browse files
passgatdtor
passgat
authored and
dtor
committed
Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros
Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250917080534.1772202-3-dario.binacchi@amarulasolutions.com Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
1 parent 6c52188 commit 05fcd78

1 file changed

Lines changed: 54 additions & 42 deletions

File tree

‎drivers/input/touchscreen/imx6ul_tsc.c‎

Lines changed: 54 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <linux/errno.h>
88
#include <linux/kernel.h>
99
#include <linux/module.h>
10+
#include <linux/bitfield.h>
1011
#include <linux/gpio/consumer.h>
1112
#include <linux/input.h>
1213
#include <linux/slab.h>
@@ -20,25 +21,23 @@
2021
#include <linux/log2.h>
2122

2223
/* ADC configuration registers field define */
23-
#define ADC_AIEN (0x1 << 7)
24+
#define ADC_AIEN BIT(7)
25+
#define ADC_ADCH_MASK GENMASK(4, 0)
2426
#define ADC_CONV_DISABLE 0x1F
25-
#define ADC_AVGE (0x1 << 5)
26-
#define ADC_CAL (0x1 << 7)
27-
#define ADC_CALF 0x2
28-
#define ADC_12BIT_MODE (0x2 << 2)
29-
#define ADC_CONV_MODE_MASK (0x3 << 2)
27+
#define ADC_AVGE BIT(5)
28+
#define ADC_CAL BIT(7)
29+
#define ADC_CALF BIT(1)
30+
#define ADC_CONV_MODE_MASK GENMASK(3, 2)
31+
#define ADC_12BIT_MODE 0x2
3032
#define ADC_IPG_CLK 0x00
31-
#define ADC_INPUT_CLK_MASK 0x3
32-
#define ADC_CLK_DIV_8 (0x03 << 5)
33-
#define ADC_CLK_DIV_MASK (0x3 << 5)
34-
#define ADC_SHORT_SAMPLE_MODE (0x0 << 4)
35-
#define ADC_SAMPLE_MODE_MASK (0x1 << 4)
36-
#define ADC_HARDWARE_TRIGGER (0x1 << 13)
37-
#define ADC_AVGS_SHIFT 14
38-
#define ADC_AVGS_MASK (0x3 << 14)
33+
#define ADC_INPUT_CLK_MASK GENMASK(1, 0)
34+
#define ADC_CLK_DIV_8 0x03
35+
#define ADC_CLK_DIV_MASK GENMASK(6, 5)
36+
#define ADC_SAMPLE_MODE BIT(4)
37+
#define ADC_HARDWARE_TRIGGER BIT(13)
38+
#define ADC_AVGS_MASK GENMASK(15, 14)
3939
#define SELECT_CHANNEL_4 0x04
4040
#define SELECT_CHANNEL_1 0x01
41-
#define DISABLE_CONVERSION_INT (0x0 << 7)
4241

4342
/* ADC registers */
4443
#define REG_ADC_HC0 0x00
@@ -65,19 +64,26 @@
6564
#define REG_TSC_DEBUG_MODE 0x70
6665
#define REG_TSC_DEBUG_MODE2 0x80
6766

67+
/* TSC_MEASURE_VALUE register field define */
68+
#define X_VALUE_MASK GENMASK(27, 16)
69+
#define Y_VALUE_MASK GENMASK(11, 0)
70+
6871
/* TSC configuration registers field define */
69-
#define DETECT_4_WIRE_MODE (0x0 << 4)
70-
#define AUTO_MEASURE 0x1
71-
#define MEASURE_SIGNAL 0x1
72-
#define DETECT_SIGNAL (0x1 << 4)
73-
#define VALID_SIGNAL (0x1 << 8)
74-
#define MEASURE_INT_EN 0x1
75-
#define MEASURE_SIG_EN 0x1
76-
#define VALID_SIG_EN (0x1 << 8)
77-
#define DE_GLITCH_2 (0x2 << 29)
78-
#define START_SENSE (0x1 << 12)
79-
#define TSC_DISABLE (0x1 << 16)
72+
#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8)
73+
#define DETECT_5_WIRE_MODE BIT(4)
74+
#define AUTO_MEASURE BIT(0)
75+
#define MEASURE_SIGNAL BIT(0)
76+
#define DETECT_SIGNAL BIT(4)
77+
#define VALID_SIGNAL BIT(8)
78+
#define MEASURE_INT_EN BIT(0)
79+
#define MEASURE_SIG_EN BIT(0)
80+
#define VALID_SIG_EN BIT(8)
81+
#define DE_GLITCH_MASK GENMASK(30, 29)
82+
#define DE_GLITCH_2 0x02
83+
#define START_SENSE BIT(12)
84+
#define TSC_DISABLE BIT(16)
8085
#define DETECT_MODE 0x2
86+
#define STATE_MACHINE_MASK GENMASK(22, 20)
8187

8288
struct imx6ul_tsc {
8389
struct device *dev;
@@ -112,19 +118,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
112118

113119
adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
114120
adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
115-
adc_cfg |= ADC_12BIT_MODE | ADC_IPG_CLK;
116-
adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK);
117-
adc_cfg |= ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE;
121+
adc_cfg |= FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) |
122+
FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK);
123+
adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE);
124+
adc_cfg |= FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8);
118125
if (tsc->average_enable) {
119126
adc_cfg &= ~ADC_AVGS_MASK;
120-
adc_cfg |= (tsc->average_select) << ADC_AVGS_SHIFT;
127+
adc_cfg |= FIELD_PREP(ADC_AVGS_MASK, tsc->average_select);
121128
}
122129
adc_cfg &= ~ADC_HARDWARE_TRIGGER;
123130
writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
124131

125132
/* enable calibration interrupt */
126133
adc_hc |= ADC_AIEN;
127-
adc_hc |= ADC_CONV_DISABLE;
134+
adc_hc |= FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE);
128135
writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
129136

130137
/* start ADC calibration */
@@ -164,19 +171,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
164171
{
165172
u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
166173

167-
adc_hc0 = DISABLE_CONVERSION_INT;
174+
adc_hc0 = FIELD_PREP(ADC_AIEN, 0);
168175
writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
169176

170-
adc_hc1 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_4;
177+
adc_hc1 = FIELD_PREP(ADC_AIEN, 0) |
178+
FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4);
171179
writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
172180

173-
adc_hc2 = DISABLE_CONVERSION_INT;
181+
adc_hc2 = FIELD_PREP(ADC_AIEN, 0);
174182
writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
175183

176-
adc_hc3 = DISABLE_CONVERSION_INT | SELECT_CHANNEL_1;
184+
adc_hc3 = FIELD_PREP(ADC_AIEN, 0) |
185+
FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1);
177186
writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
178187

179-
adc_hc4 = DISABLE_CONVERSION_INT;
188+
adc_hc4 = FIELD_PREP(ADC_AIEN, 0);
180189
writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
181190
}
182191

@@ -188,13 +197,16 @@ static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
188197
static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
189198
{
190199
u32 basic_setting = 0;
200+
u32 debug_mode2;
191201
u32 start;
192202

193-
basic_setting |= tsc->measure_delay_time << 8;
194-
basic_setting |= DETECT_4_WIRE_MODE | AUTO_MEASURE;
203+
basic_setting |= FIELD_PREP(MEASURE_DELAY_TIME_MASK,
204+
tsc->measure_delay_time);
205+
basic_setting |= AUTO_MEASURE;
195206
writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING);
196207

197-
writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
208+
debug_mode2 = FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2);
209+
writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
198210

199211
writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
200212
writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
@@ -250,7 +262,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
250262

251263
usleep_range(200, 400);
252264
debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
253-
state_machine = (debug_mode2 >> 20) & 0x7;
265+
state_machine = FIELD_GET(STATE_MACHINE_MASK, debug_mode2);
254266
} while (state_machine != DETECT_MODE);
255267

256268
usleep_range(200, 400);
@@ -278,8 +290,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
278290

279291
if (status & MEASURE_SIGNAL) {
280292
value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
281-
x = (value >> 16) & 0x0fff;
282-
y = value & 0x0fff;
293+
x = FIELD_GET(X_VALUE_MASK, value);
294+
y = FIELD_GET(Y_VALUE_MASK, value);
283295

284296
/*
285297
* In detect mode, we can get the xnur gpio value,

0 commit comments

Comments
 (0)