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akhilpo-qcomRob Clark
akhilpo-qcom
authored and
Rob Clark
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drm/msm/a8xx: Add support for Adreno 840 GPU
Adreno 840 present in Kaanapali SoC is the second generation GPU in A8x family. It comes in 2 variants with either 2 or 3 Slices. This is in addition to the SKUs supported based on the GPU FMAX. Add the necessary register configurations to the catalog and enable support for it. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689022/ Message-ID: <20251118-kaana-gpu-support-v4-16-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent 16201a1 commit 0700b9f

5 files changed

Lines changed: 174 additions & 1 deletion

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‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1628,11 +1628,170 @@ static const struct adreno_info a7xx_gpus[] = {
16281628
};
16291629
DECLARE_ADRENO_GPULIST(a7xx);
16301630

1631+
static const struct adreno_reglist_pipe a840_nonctxt_regs[] = {
1632+
{ REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) },
1633+
{ REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) },
1634+
{ REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0x00200000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1635+
{ REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1636+
{ REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1637+
{ REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) | BIT(PIPE_BR) },
1638+
{ REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BV) | BIT(PIPE_BR) },
1639+
{ REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) },
1640+
{ REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1641+
{ REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1642+
/* Disable Dead Draw Merge scheme on RB-HLSQ */
1643+
{ REG_A6XX_RB_RBP_CNTL, BIT(5), BIT(PIPE_BV) | BIT(PIPE_BR) },
1644+
{ REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) },
1645+
/* Partially enable perf clear, Disable DINT to c/z be data forwarding */
1646+
{ REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x00002200, BIT(PIPE_BR) },
1647+
{ REG_A8XX_RB_GC_GMEM_PROTECT, 0x12000000, BIT(PIPE_BR) },
1648+
{ REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) },
1649+
{ REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) },
1650+
{ REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1651+
{ REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) },
1652+
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_OVERRIDE, 0x70809060, BIT(PIPE_NONE) },
1653+
{ REG_A8XX_RBBM_POWER_UP_RESET_SW_BV_OVERRIDE, 0x30000000, BIT(PIPE_NONE) },
1654+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) },
1655+
{ REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) },
1656+
{ REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, 0x0fffffff, BIT(PIPE_NONE) },
1657+
{ REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) },
1658+
{ REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) },
1659+
/* Disable mode_switch optimization in UMAS */
1660+
{ REG_A6XX_SP_CHICKEN_BITS, BIT(24) | BIT(26), BIT(PIPE_NONE) },
1661+
/* Disable LPAC large-LM mode */
1662+
{ REG_A8XX_SP_SS_CHICKEN_BITS_0, BIT(3), BIT(PIPE_NONE) },
1663+
/* Disable PS out of order retire */
1664+
{ REG_A7XX_SP_CHICKEN_BITS_2, 0x00c21800, BIT(PIPE_NONE) },
1665+
{ REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) },
1666+
/* Disable SP2TP info attribute */
1667+
{ REG_A8XX_SP_CHICKEN_BITS_4, 0x00000002, BIT(PIPE_NONE) },
1668+
{ REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) },
1669+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, BIT(14), BIT(PIPE_NONE) },
1670+
/* Ignore HLSQ shared constant feedback from SP */
1671+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, BIT(17), BIT(PIPE_NONE) },
1672+
/* Disable CS dead batch merge */
1673+
{ REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_2, BIT(24), BIT(PIPE_NONE) },
1674+
{ REG_A8XX_SP_HLSQ_DBG_ECO_CNTL_3, BIT(7), BIT(PIPE_NONE) },
1675+
{ REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) },
1676+
{ REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) },
1677+
{ REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10100000, BIT(PIPE_NONE) },
1678+
/* BIT(26): Disable final clamp for bicubic filtering */
1679+
{ REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) },
1680+
{ REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) },
1681+
{ REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) },
1682+
{ REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) },
1683+
{ REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) },
1684+
{ REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) },
1685+
{ REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) },
1686+
{ REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) },
1687+
{ REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) },
1688+
{ REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1689+
{ REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00000020, BIT(PIPE_BV) | BIT(PIPE_BR) },
1690+
{ REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR) },
1691+
{ },
1692+
};
1693+
1694+
static const u32 a840_protect_regs[] = {
1695+
A6XX_PROTECT_RDONLY(0x00008, 0x039b),
1696+
A6XX_PROTECT_RDONLY(0x003b4, 0x008b),
1697+
A6XX_PROTECT_NORDWR(0x00440, 0x001f),
1698+
A6XX_PROTECT_RDONLY(0x00580, 0x005f),
1699+
A6XX_PROTECT_NORDWR(0x005e0, 0x011f),
1700+
A6XX_PROTECT_RDONLY(0x0074a, 0x0005),
1701+
A6XX_PROTECT_RDONLY(0x00759, 0x001b),
1702+
A6XX_PROTECT_NORDWR(0x00775, 0x000a),
1703+
A6XX_PROTECT_RDONLY(0x00789, 0x0000),
1704+
A6XX_PROTECT_RDONLY(0x0078c, 0x0013),
1705+
A6XX_PROTECT_NORDWR(0x00800, 0x0029),
1706+
A6XX_PROTECT_NORDWR(0x00837, 0x00af),
1707+
A6XX_PROTECT_RDONLY(0x008e7, 0x00c9),
1708+
A6XX_PROTECT_NORDWR(0x008ec, 0x00c3),
1709+
A6XX_PROTECT_NORDWR(0x009b1, 0x0250),
1710+
A6XX_PROTECT_NORDWR(0x00c07, 0x0008),
1711+
A6XX_PROTECT_RDONLY(0x00ce0, 0x0001),
1712+
A6XX_PROTECT_RDONLY(0x00df0, 0x0000),
1713+
A6XX_PROTECT_NORDWR(0x00df1, 0x0000),
1714+
A6XX_PROTECT_NORDWR(0x00e01, 0x0000),
1715+
A6XX_PROTECT_NORDWR(0x00e03, 0x1fff),
1716+
A6XX_PROTECT_NORDWR(0x03c00, 0x00c5),
1717+
A6XX_PROTECT_RDONLY(0x03cc6, 0x0039),
1718+
A6XX_PROTECT_NORDWR(0x03d00, 0x1fff),
1719+
A6XX_PROTECT_NORDWR(0x08600, 0x01ff),
1720+
A6XX_PROTECT_NORDWR(0x08e00, 0x00ff),
1721+
A6XX_PROTECT_RDONLY(0x08f00, 0x0000),
1722+
A6XX_PROTECT_NORDWR(0x08f01, 0x01be),
1723+
A6XX_PROTECT_NORDWR(0x09600, 0x01ff),
1724+
A6XX_PROTECT_RDONLY(0x0981a, 0x02e5),
1725+
A6XX_PROTECT_NORDWR(0x09e00, 0x01ff),
1726+
A6XX_PROTECT_NORDWR(0x0a600, 0x01ff),
1727+
A6XX_PROTECT_NORDWR(0x0a82e, 0x0000),
1728+
A6XX_PROTECT_NORDWR(0x0ae00, 0x0000),
1729+
A6XX_PROTECT_NORDWR(0x0ae02, 0x0004),
1730+
A6XX_PROTECT_NORDWR(0x0ae08, 0x0006),
1731+
A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf),
1732+
A6XX_PROTECT_RDONLY(0x0aed0, 0x002f),
1733+
A6XX_PROTECT_NORDWR(0x0af00, 0x027f),
1734+
A6XX_PROTECT_NORDWR(0x0b600, 0x1fff),
1735+
A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff),
1736+
A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
1737+
A6XX_PROTECT_NORDWR(0x18400, 0x003f),
1738+
A6XX_PROTECT_RDONLY(0x18440, 0x013f),
1739+
A6XX_PROTECT_NORDWR(0x18580, 0x1fff),
1740+
A6XX_PROTECT_NORDWR(0x1b400, 0x1fff),
1741+
A6XX_PROTECT_NORDWR(0x1f400, 0x0477),
1742+
A6XX_PROTECT_RDONLY(0x1f878, 0x0507),
1743+
A6XX_PROTECT_NORDWR(0x1f930, 0x0329),
1744+
A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff),
1745+
A6XX_PROTECT_NORDWR(0x27800, 0x007f),
1746+
A6XX_PROTECT_RDONLY(0x27880, 0x0385),
1747+
A6XX_PROTECT_NORDWR(0x27882, 0x0009),
1748+
A6XX_PROTECT_NORDWR(0x27c06, 0x0000),
1749+
};
1750+
DECLARE_ADRENO_PROTECT(a840_protect, 15);
1751+
1752+
static const struct adreno_info a8xx_gpus[] = {
1753+
{
1754+
.chip_ids = ADRENO_CHIP_IDS(0x44050a01),
1755+
.family = ADRENO_8XX_GEN2,
1756+
.fw = {
1757+
[ADRENO_FW_SQE] = "gen80200_sqe.fw",
1758+
[ADRENO_FW_GMU] = "gen80200_gmu.bin",
1759+
[ADRENO_FW_AQE] = "gen80200_aqe.fw",
1760+
},
1761+
.gmem = 18 * SZ_1M,
1762+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
1763+
.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
1764+
ADRENO_QUIRK_HAS_HW_APRIV,
1765+
.funcs = &a8xx_gpu_funcs,
1766+
.a6xx = &(const struct a6xx_info) {
1767+
.protect = &a840_protect,
1768+
.nonctxt_reglist = a840_nonctxt_regs,
1769+
.max_slices = 3,
1770+
.gmu_chipid = 0x8020100,
1771+
.bcms = (const struct a6xx_bcm[]) {
1772+
{ .name = "SH0", .buswidth = 16 },
1773+
{ .name = "MC0", .buswidth = 4 },
1774+
{
1775+
.name = "ACV",
1776+
.fixed = true,
1777+
.perfmode = BIT(2),
1778+
.perfmode_bw = 10687500,
1779+
},
1780+
{ /* sentinel */ },
1781+
},
1782+
},
1783+
.preempt_record_size = 19708 * SZ_1K,
1784+
}
1785+
};
1786+
1787+
DECLARE_ADRENO_GPULIST(a8xx);
1788+
16311789
static inline __always_unused void __build_asserts(void)
16321790
{
16331791
BUILD_BUG_ON(a630_protect.count > a630_protect.count_max);
16341792
BUILD_BUG_ON(a650_protect.count > a650_protect.count_max);
16351793
BUILD_BUG_ON(a660_protect.count > a660_protect.count_max);
16361794
BUILD_BUG_ON(a690_protect.count > a690_protect.count_max);
16371795
BUILD_BUG_ON(a730_protect.count > a730_protect.count_max);
1796+
BUILD_BUG_ON(a840_protect.count > a840_protect.count_max);
16381797
}

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -601,16 +601,22 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
601601

602602
static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
603603
{
604+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
605+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
606+
u32 bitmask = BIT(16);
604607
int ret;
605608
u32 val;
606609

607610
if (test_and_clear_bit(GMU_STATUS_FW_START, &gmu->status))
608611
return;
609612

613+
if (adreno_is_a840(adreno_gpu))
614+
bitmask = BIT(30);
615+
610616
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
611617

612618
ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
613-
val, val & (1 << 16), 100, 10000);
619+
val, val & bitmask, 100, 10000);
614620
if (ret)
615621
DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
616622

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,7 @@ struct a7xx_cp_smmu_info {
228228
extern const struct adreno_gpu_funcs a6xx_gpu_funcs;
229229
extern const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs;
230230
extern const struct adreno_gpu_funcs a7xx_gpu_funcs;
231+
extern const struct adreno_gpu_funcs a8xx_gpu_funcs;
231232

232233
static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
233234
{

‎drivers/gpu/drm/msm/adreno/adreno_device.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ extern const struct adreno_gpulist a4xx_gpulist;
3434
extern const struct adreno_gpulist a5xx_gpulist;
3535
extern const struct adreno_gpulist a6xx_gpulist;
3636
extern const struct adreno_gpulist a7xx_gpulist;
37+
extern const struct adreno_gpulist a8xx_gpulist;
3738

3839
static const struct adreno_gpulist *gpulists[] = {
3940
&a2xx_gpulist,
@@ -42,6 +43,7 @@ static const struct adreno_gpulist *gpulists[] = {
4243
&a5xx_gpulist,
4344
&a6xx_gpulist,
4445
&a7xx_gpulist,
46+
&a8xx_gpulist,
4547
};
4648

4749
static const struct adreno_info *adreno_info(uint32_t chip_id)

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -580,6 +580,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gpu)
580580
return gpu->info->family >= ADRENO_8XX_GEN1;
581581
}
582582

583+
static inline int adreno_is_a840(struct adreno_gpu *gpu)
584+
{
585+
return gpu->info->chip_ids[0] == 0x44050a01;
586+
}
587+
583588
/* Put vm_start above 32b to catch issues with not setting xyz_BASE_HI */
584589
#define ADRENO_VM_START 0x100000000ULL
585590
u64 adreno_private_vm_size(struct msm_gpu *gpu);

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