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hoshinolinajannau
hoshinolina
authored and
jannau
committed
drm/asahi: Convert more ranges to Range<>
Signed-off-by: Asahi Lina <lina@asahilina.net>
1 parent be5a257 commit 0b56dab

5 files changed

Lines changed: 93 additions & 116 deletions

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‎drivers/gpu/drm/asahi/alloc.rs‎

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -19,13 +19,15 @@ use crate::driver::{AsahiDevRef, AsahiDevice};
1919
use crate::fw::types::Zeroable;
2020
use crate::mmu;
2121
use crate::object::{GpuArray, GpuObject, GpuOnlyArray, GpuStruct, GpuWeakPointer};
22+
use crate::util::RangeExt;
2223

2324
use core::cmp::Ordering;
2425
use core::fmt;
2526
use core::fmt::{Debug, Formatter};
2627
use core::marker::PhantomData;
2728
use core::mem;
2829
use core::mem::MaybeUninit;
30+
use core::ops::Range;
2931
use core::ptr::NonNull;
3032

3133
const DEBUG_CLASS: DebugFlags = DebugFlags::Alloc;
@@ -491,8 +493,7 @@ impl RawAllocation for SimpleAllocation {
491493
/// GPU's idea of object size what we expect.
492494
pub(crate) struct SimpleAllocator {
493495
dev: AsahiDevRef,
494-
start: u64,
495-
end: u64,
496+
range: Range<u64>,
496497
prot: u32,
497498
vm: mmu::Vm,
498499
min_align: usize,
@@ -506,8 +507,7 @@ impl SimpleAllocator {
506507
pub(crate) fn new(
507508
dev: &AsahiDevice,
508509
vm: &mmu::Vm,
509-
start: u64,
510-
end: u64,
510+
range: Range<u64>,
511511
min_align: usize,
512512
prot: u32,
513513
_block_size: usize,
@@ -521,8 +521,7 @@ impl SimpleAllocator {
521521
Ok(SimpleAllocator {
522522
dev: dev.into(),
523523
vm: vm.clone(),
524-
start,
525-
end,
524+
range,
526525
prot,
527526
min_align,
528527
cpu_maps,
@@ -567,8 +566,7 @@ impl Allocator for SimpleAllocator {
567566
}
568567
let mapping = obj.map_into_range(
569568
&self.vm,
570-
self.start,
571-
self.end,
569+
self.range.clone(),
572570
self.min_align.max(mmu::UAT_PGSZ) as u64,
573571
self.prot,
574572
true,
@@ -709,8 +707,7 @@ struct HeapAllocatorInner {
709707
/// never shrinks it.
710708
pub(crate) struct HeapAllocator {
711709
dev: AsahiDevRef,
712-
start: u64,
713-
end: u64,
710+
range: Range<u64>,
714711
top: u64,
715712
prot: u32,
716713
vm: mmu::Vm,
@@ -730,8 +727,7 @@ impl HeapAllocator {
730727
pub(crate) fn new(
731728
dev: &AsahiDevice,
732729
vm: &mmu::Vm,
733-
start: u64,
734-
end: u64,
730+
range: Range<u64>,
735731
min_align: usize,
736732
prot: u32,
737733
block_size: usize,
@@ -762,14 +758,13 @@ impl HeapAllocator {
762758
total_garbage: 0,
763759
};
764760

765-
let mm = mm::Allocator::new(start, end - start + 1, inner)?;
761+
let mm = mm::Allocator::new(range.start, range.range(), inner)?;
766762

767763
Ok(HeapAllocator {
768764
dev: dev.into(),
769765
vm: vm.clone(),
770-
start,
771-
end,
772-
top: start,
766+
top: range.start,
767+
range,
773768
prot,
774769
min_align,
775770
block_size: block_size.max(min_align),
@@ -806,7 +801,7 @@ impl HeapAllocator {
806801
size_aligned,
807802
);
808803

809-
if self.top.saturating_add(size_aligned as u64) >= self.end {
804+
if self.top.saturating_add(size_aligned as u64) > self.range.end {
810805
dev_err!(
811806
self.dev.as_ref(),
812807
"HeapAllocator[{}]::add_block: Exhausted VA space\n",
@@ -892,7 +887,7 @@ impl HeapAllocator {
892887
&self.dev,
893888
"{} Heap: grow to {} bytes\n",
894889
&*self.name,
895-
self.top - self.start
890+
self.top - self.range.start
896891
);
897892

898893
Ok(())

‎drivers/gpu/drm/asahi/file.rs‎

Lines changed: 28 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -314,30 +314,34 @@ impl File {
314314
file_id,
315315
id
316316
);
317-
let ualloc = Arc::pin_init(Mutex::new(alloc::DefaultAllocator::new(
318-
device,
319-
&vm,
320-
VM_DRV_GPU_START,
321-
VM_DRV_GPU_END,
322-
buffer::PAGE_SIZE,
323-
mmu::PROT_GPU_SHARED_RW,
324-
512 * 1024,
325-
true,
326-
fmt!("File {} VM {} GPU Shared", file_id, id),
327-
false,
328-
)?))?;
329-
let ualloc_priv = Arc::pin_init(Mutex::new(alloc::DefaultAllocator::new(
330-
device,
331-
&vm,
332-
VM_DRV_GPUFW_START,
333-
VM_DRV_GPUFW_END,
334-
buffer::PAGE_SIZE,
335-
mmu::PROT_GPU_FW_PRIV_RW,
336-
64 * 1024,
337-
true,
338-
fmt!("File {} VM {} GPU FW Private", file_id, id),
339-
false,
340-
)?))?;
317+
let ualloc = Arc::pin_init(
318+
Mutex::new(alloc::DefaultAllocator::new(
319+
device,
320+
&vm,
321+
VM_DRV_GPU_START..VM_DRV_GPU_END,
322+
buffer::PAGE_SIZE,
323+
mmu::PROT_GPU_SHARED_RW,
324+
512 * 1024,
325+
true,
326+
fmt!("File {} VM {} GPU Shared", file_id, id),
327+
false,
328+
)?),
329+
GFP_KERNEL,
330+
)?;
331+
let ualloc_priv = Arc::pin_init(
332+
Mutex::new(alloc::DefaultAllocator::new(
333+
device,
334+
&vm,
335+
VM_DRV_GPUFW_START..VM_DRV_GPUFW_END,
336+
buffer::PAGE_SIZE,
337+
mmu::PROT_GPU_FW_PRIV_RW,
338+
64 * 1024,
339+
true,
340+
fmt!("File {} VM {} GPU FW Private", file_id, id),
341+
false,
342+
)?),
343+
GFP_KERNEL,
344+
)?;
341345

342346
mod_dev_dbg!(
343347
device,

‎drivers/gpu/drm/asahi/gem.rs‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ use kernel::{
1616

1717
use kernel::drm::gem::BaseObject;
1818

19+
use core::ops::Range;
1920
use core::sync::atomic::{AtomicU64, Ordering};
2021

2122
use crate::{debug::*, driver::AsahiDevice, file, file::DrmFile, mmu, util::*};
@@ -76,8 +77,7 @@ impl ObjectRef {
7677
pub(crate) fn map_into_range(
7778
&mut self,
7879
vm: &crate::mmu::Vm,
79-
start: u64,
80-
end: u64,
80+
range: Range<u64>,
8181
alignment: u64,
8282
prot: u32,
8383
guard: bool,
@@ -88,15 +88,7 @@ impl ObjectRef {
8888
return Err(EINVAL);
8989
}
9090

91-
vm.map_in_range(
92-
self.gem.size(),
93-
&self.gem,
94-
alignment,
95-
start,
96-
end,
97-
prot,
98-
guard,
99-
)
91+
vm.map_in_range(self.gem.size(), &self.gem, alignment, range, prot, guard)
10092
}
10193

10294
/// Maps an object into a given `Vm` at a specific address.

‎drivers/gpu/drm/asahi/gpu.rs‎

Lines changed: 46 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
//! itself with version dependence.
1313
1414
use core::any::Any;
15+
use core::ops::Range;
1516
use core::sync::atomic::{AtomicBool, AtomicU64, Ordering};
1617
use core::time::Duration;
1718

@@ -68,33 +69,19 @@ const DOORBELL_DEVCTRL: u64 = 0x11;
6869

6970
// Upper kernel half VA address ranges.
7071
/// Private (cached) firmware structure VA range base.
71-
const IOVA_KERN_PRIV_BASE: u64 = 0xffffffa000000000;
72-
/// Private (cached) firmware structure VA range top.
73-
const IOVA_KERN_PRIV_TOP: u64 = 0xffffffa5ffffffff;
72+
const IOVA_KERN_PRIV_RANGE: Range<u64> = 0xffffffa000000000..0xffffffa600000000;
7473
/// Private (cached) GPU-RO firmware structure VA range base.
75-
const IOVA_KERN_GPU_RO_BASE: u64 = 0xffffffa600000000;
76-
/// Private (cached) GPU-RO firmware structure VA range top.
77-
const IOVA_KERN_GPU_RO_TOP: u64 = 0xffffffa7ffffffff;
74+
const IOVA_KERN_GPU_RO_RANGE: Range<u64> = 0xffffffa600000000..0xffffffa800000000;
7875
/// Shared (uncached) firmware structure VA range base.
79-
const IOVA_KERN_SHARED_BASE: u64 = 0xffffffa800000000;
80-
/// Shared (uncached) firmware structure VA range top.
81-
const IOVA_KERN_SHARED_TOP: u64 = 0xffffffa9ffffffff;
76+
const IOVA_KERN_SHARED_RANGE: Range<u64> = 0xffffffa800000000..0xffffffaa00000000;
8277
/// Shared (uncached) read-only firmware structure VA range base.
83-
const IOVA_KERN_SHARED_RO_BASE: u64 = 0xffffffaa00000000;
84-
/// Shared (uncached) read-only firmware structure VA range top.
85-
const IOVA_KERN_SHARED_RO_TOP: u64 = 0xffffffabffffffff;
78+
const IOVA_KERN_SHARED_RO_RANGE: Range<u64> = 0xffffffaa00000000..0xffffffac00000000;
8679
/// GPU/FW shared structure VA range base.
87-
const IOVA_KERN_GPU_BASE: u64 = 0xffffffac00000000;
88-
/// GPU/FW shared structure VA range top.
89-
const IOVA_KERN_GPU_TOP: u64 = 0xffffffadffffffff;
80+
const IOVA_KERN_GPU_RANGE: Range<u64> = 0xffffffac00000000..0xffffffae00000000;
9081
/// GPU/FW shared structure VA range base.
91-
const IOVA_KERN_RTKIT_BASE: u64 = 0xffffffae00000000;
92-
/// GPU/FW shared structure VA range top.
93-
const IOVA_KERN_RTKIT_TOP: u64 = 0xffffffae0fffffff;
82+
const IOVA_KERN_RTKIT_RANGE: Range<u64> = 0xffffffae00000000..0xffffffae10000000;
9483
/// FW MMIO VA range base.
95-
const IOVA_KERN_MMIO_BASE: u64 = 0xffffffaf00000000;
96-
/// FW MMIO VA range top.
97-
const IOVA_KERN_MMIO_TOP: u64 = 0xffffffafffffffff;
84+
const IOVA_KERN_MMIO_RANGE: Range<u64> = 0xffffffaf00000000..0xffffffb000000000;
9885

9986
/// GPU/FW buffer manager control address (context 0 low)
10087
pub(crate) const IOVA_KERN_GPU_BUFMGR_LOW: u64 = 0x20_0000_0000;
@@ -354,8 +341,7 @@ impl rtkit::Operations for GpuManager::ver {
354341
obj.vmap()?;
355342
let mapping = obj.map_into_range(
356343
data.uat.kernel_vm(),
357-
IOVA_KERN_RTKIT_BASE,
358-
IOVA_KERN_RTKIT_TOP,
344+
IOVA_KERN_RTKIT_RANGE,
359345
mmu::UAT_PGSZ as u64,
360346
mmu::PROT_FW_SHARED_RW,
361347
true,
@@ -381,8 +367,7 @@ impl GpuManager::ver {
381367
private: alloc::DefaultAllocator::new(
382368
dev,
383369
uat.kernel_vm(),
384-
IOVA_KERN_PRIV_BASE,
385-
IOVA_KERN_PRIV_TOP,
370+
IOVA_KERN_PRIV_RANGE,
386371
0x80,
387372
mmu::PROT_FW_PRIV_RW,
388373
1024 * 1024,
@@ -393,8 +378,7 @@ impl GpuManager::ver {
393378
shared: alloc::DefaultAllocator::new(
394379
dev,
395380
uat.kernel_vm(),
396-
IOVA_KERN_SHARED_BASE,
397-
IOVA_KERN_SHARED_TOP,
381+
IOVA_KERN_SHARED_RANGE,
398382
0x80,
399383
mmu::PROT_FW_SHARED_RW,
400384
1024 * 1024,
@@ -405,8 +389,7 @@ impl GpuManager::ver {
405389
shared_ro: alloc::DefaultAllocator::new(
406390
dev,
407391
uat.kernel_vm(),
408-
IOVA_KERN_SHARED_RO_BASE,
409-
IOVA_KERN_SHARED_RO_TOP,
392+
IOVA_KERN_SHARED_RO_RANGE,
410393
0x80,
411394
mmu::PROT_FW_SHARED_RO,
412395
64 * 1024,
@@ -417,8 +400,7 @@ impl GpuManager::ver {
417400
gpu: alloc::DefaultAllocator::new(
418401
dev,
419402
uat.kernel_vm(),
420-
IOVA_KERN_GPU_BASE,
421-
IOVA_KERN_GPU_TOP,
403+
IOVA_KERN_GPU_RANGE,
422404
0x80,
423405
mmu::PROT_GPU_FW_SHARED_RW,
424406
64 * 1024,
@@ -429,8 +411,7 @@ impl GpuManager::ver {
429411
gpu_ro: alloc::DefaultAllocator::new(
430412
dev,
431413
uat.kernel_vm(),
432-
IOVA_KERN_GPU_RO_BASE,
433-
IOVA_KERN_GPU_RO_TOP,
414+
IOVA_KERN_GPU_RO_RANGE,
434415
0x80,
435416
mmu::PROT_GPU_RO_FW_PRIV_RW,
436417
1024 * 1024,
@@ -592,7 +573,7 @@ impl GpuManager::ver {
592573
let addr = *next_ref;
593574
let next = addr + (size + mmu::UAT_PGSZ) as u64;
594575

595-
assert!(next - 1 <= IOVA_KERN_MMIO_TOP);
576+
assert!(next <= IOVA_KERN_MMIO_RANGE.end);
596577

597578
*next_ref = next;
598579

@@ -702,31 +683,37 @@ impl GpuManager::ver {
702683
)?;
703684

704685
let alloc_ref = &mut alloc;
705-
let tx_channels = Box::init(try_init!(TxChannels::ver {
706-
device_control: channel::DeviceControlChannel::ver::new(dev, alloc_ref)?,
707-
}))?;
708-
709-
let x = UniqueArc::pin_init(try_pin_init!(GpuManager::ver {
710-
dev: dev.into(),
711-
cfg,
712-
dyncfg: *dyncfg,
713-
initdata: *initdata,
714-
uat: *uat,
715-
io_mappings: Vec::new(),
716-
next_mmio_iova: IOVA_KERN_MMIO_BASE,
717-
rtkit <- Mutex::new_named(None, c_str!("rtkit")),
718-
crashed: AtomicBool::new(false),
719-
event_manager,
720-
alloc <- Mutex::new_named(alloc, c_str!("alloc")),
721-
fwctl_channel <- Mutex::new_named(fwctl_channel, c_str!("fwctl_channel")),
722-
rx_channels <- Mutex::new_named(*rx_channels, c_str!("rx_channels")),
723-
tx_channels <- Mutex::new_named(*tx_channels, c_str!("tx_channels")),
724-
pipes,
725-
buffer_mgr,
726-
ids: Default::default(),
727-
garbage_work <- Mutex::new_named(Vec::new(), c_str!("garbage_work")),
728-
garbage_contexts <- Mutex::new_named(Vec::new(), c_str!("garbage_contexts")),
729-
}))?;
686+
let tx_channels = Box::init(
687+
try_init!(TxChannels::ver {
688+
device_control: channel::DeviceControlChannel::ver::new(dev, alloc_ref)?,
689+
}),
690+
GFP_KERNEL,
691+
)?;
692+
693+
let x = UniqueArc::pin_init(
694+
try_pin_init!(GpuManager::ver {
695+
dev: dev.into(),
696+
cfg,
697+
dyncfg: *dyncfg,
698+
initdata: *initdata,
699+
uat: *uat,
700+
io_mappings: Vec::new(),
701+
next_mmio_iova: IOVA_KERN_MMIO_RANGE.start,
702+
rtkit <- Mutex::new_named(None, c_str!("rtkit")),
703+
crashed: AtomicBool::new(false),
704+
event_manager,
705+
alloc <- Mutex::new_named(alloc, c_str!("alloc")),
706+
fwctl_channel <- Mutex::new_named(fwctl_channel, c_str!("fwctl_channel")),
707+
rx_channels <- Mutex::new_named(*rx_channels, c_str!("rx_channels")),
708+
tx_channels <- Mutex::new_named(*tx_channels, c_str!("tx_channels")),
709+
pipes,
710+
buffer_mgr,
711+
ids: Default::default(),
712+
garbage_work <- Mutex::new_named(Vec::new(), c_str!("garbage_work")),
713+
garbage_contexts <- Mutex::new_named(Vec::new(), c_str!("garbage_contexts")),
714+
}),
715+
GFP_KERNEL,
716+
)?;
730717

731718
Ok(x)
732719
}

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