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masneyb
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clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Note that prior to running the Coccinelle, clk_alpha_pll_postdiv_round_ro_rate() was renamed to clk_alpha_pll_postdiv_ro_round_rate(). Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/r/20250828-clk-round-rate-v2-v1-2-b97ec8ba6cc4@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Lines changed: 77 additions & 59 deletions

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‎drivers/clk/qcom/clk-alpha-pll.c‎

Lines changed: 77 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -849,22 +849,25 @@ static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
849849
clk_alpha_pll_hwfsm_is_enabled);
850850
}
851851

852-
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
853-
unsigned long *prate)
852+
static int clk_alpha_pll_determine_rate(struct clk_hw *hw,
853+
struct clk_rate_request *req)
854854
{
855855
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
856856
u32 l, alpha_width = pll_alpha_width(pll);
857857
u64 a;
858858
unsigned long min_freq, max_freq;
859859

860-
rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
861-
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
862-
return rate;
860+
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
861+
&a, alpha_width);
862+
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
863+
return 0;
863864

864865
min_freq = pll->vco_table[0].min_freq;
865866
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
866867

867-
return clamp(rate, min_freq, max_freq);
868+
req->rate = clamp(req->rate, min_freq, max_freq);
869+
870+
return 0;
868871
}
869872

870873
void clk_huayra_2290_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
@@ -1048,12 +1051,15 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
10481051
return 0;
10491052
}
10501053

1051-
static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
1052-
unsigned long *prate)
1054+
static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
1055+
struct clk_rate_request *req)
10531056
{
10541057
u32 l, a;
10551058

1056-
return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
1059+
req->rate = alpha_huayra_pll_round_rate(req->rate,
1060+
req->best_parent_rate, &l, &a);
1061+
1062+
return 0;
10571063
}
10581064

10591065
static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@@ -1175,7 +1181,7 @@ const struct clk_ops clk_alpha_pll_ops = {
11751181
.disable = clk_alpha_pll_disable,
11761182
.is_enabled = clk_alpha_pll_is_enabled,
11771183
.recalc_rate = clk_alpha_pll_recalc_rate,
1178-
.round_rate = clk_alpha_pll_round_rate,
1184+
.determine_rate = clk_alpha_pll_determine_rate,
11791185
.set_rate = clk_alpha_pll_set_rate,
11801186
};
11811187
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
@@ -1185,7 +1191,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = {
11851191
.disable = clk_alpha_pll_disable,
11861192
.is_enabled = clk_alpha_pll_is_enabled,
11871193
.recalc_rate = alpha_pll_huayra_recalc_rate,
1188-
.round_rate = alpha_pll_huayra_round_rate,
1194+
.determine_rate = alpha_pll_huayra_determine_rate,
11891195
.set_rate = alpha_pll_huayra_set_rate,
11901196
};
11911197
EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
@@ -1195,7 +1201,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
11951201
.disable = clk_alpha_pll_hwfsm_disable,
11961202
.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
11971203
.recalc_rate = clk_alpha_pll_recalc_rate,
1198-
.round_rate = clk_alpha_pll_round_rate,
1204+
.determine_rate = clk_alpha_pll_determine_rate,
11991205
.set_rate = clk_alpha_pll_hwfsm_set_rate,
12001206
};
12011207
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -1205,7 +1211,7 @@ const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
12051211
.disable = clk_trion_pll_disable,
12061212
.is_enabled = clk_trion_pll_is_enabled,
12071213
.recalc_rate = clk_trion_pll_recalc_rate,
1208-
.round_rate = clk_alpha_pll_round_rate,
1214+
.determine_rate = clk_alpha_pll_determine_rate,
12091215
};
12101216
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
12111217

@@ -1240,9 +1246,8 @@ static const struct clk_div_table clk_alpha_2bit_div_table[] = {
12401246
{ }
12411247
};
12421248

1243-
static long
1244-
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1245-
unsigned long *prate)
1249+
static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw,
1250+
struct clk_rate_request *req)
12461251
{
12471252
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
12481253
const struct clk_div_table *table;
@@ -1252,13 +1257,15 @@ clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
12521257
else
12531258
table = clk_alpha_div_table;
12541259

1255-
return divider_round_rate(hw, rate, prate, table,
1256-
pll->width, CLK_DIVIDER_POWER_OF_TWO);
1260+
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
1261+
table, pll->width,
1262+
CLK_DIVIDER_POWER_OF_TWO);
1263+
1264+
return 0;
12571265
}
12581266

1259-
static long
1260-
clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1261-
unsigned long *prate)
1267+
static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw,
1268+
struct clk_rate_request *req)
12621269
{
12631270
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
12641271
u32 ctl, div;
@@ -1270,9 +1277,12 @@ clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
12701277
div = 1 << fls(ctl);
12711278

12721279
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1273-
*prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1280+
req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
1281+
div * req->rate);
1282+
1283+
req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div);
12741284

1275-
return DIV_ROUND_UP_ULL((u64)*prate, div);
1285+
return 0;
12761286
}
12771287

12781288
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -1291,13 +1301,13 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
12911301

12921302
const struct clk_ops clk_alpha_pll_postdiv_ops = {
12931303
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1294-
.round_rate = clk_alpha_pll_postdiv_round_rate,
1304+
.determine_rate = clk_alpha_pll_postdiv_determine_rate,
12951305
.set_rate = clk_alpha_pll_postdiv_set_rate,
12961306
};
12971307
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
12981308

12991309
const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1300-
.round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1310+
.determine_rate = clk_alpha_pll_postdiv_ro_determine_rate,
13011311
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
13021312
};
13031313
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
@@ -1542,7 +1552,7 @@ const struct clk_ops clk_alpha_pll_fabia_ops = {
15421552
.is_enabled = clk_alpha_pll_is_enabled,
15431553
.set_rate = alpha_pll_fabia_set_rate,
15441554
.recalc_rate = alpha_pll_fabia_recalc_rate,
1545-
.round_rate = clk_alpha_pll_round_rate,
1555+
.determine_rate = clk_alpha_pll_determine_rate,
15461556
};
15471557
EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
15481558

@@ -1551,7 +1561,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
15511561
.disable = alpha_pll_fabia_disable,
15521562
.is_enabled = clk_alpha_pll_is_enabled,
15531563
.recalc_rate = alpha_pll_fabia_recalc_rate,
1554-
.round_rate = clk_alpha_pll_round_rate,
1564+
.determine_rate = clk_alpha_pll_determine_rate,
15551565
};
15561566
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
15571567

@@ -1602,14 +1612,16 @@ clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
16021612
return (parent_rate / div);
16031613
}
16041614

1605-
static long
1606-
clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1607-
unsigned long *prate)
1615+
static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw,
1616+
struct clk_rate_request *req)
16081617
{
16091618
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
16101619

1611-
return divider_round_rate(hw, rate, prate, pll->post_div_table,
1612-
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1620+
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
1621+
pll->post_div_table,
1622+
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1623+
1624+
return 0;
16131625
};
16141626

16151627
static int
@@ -1635,18 +1647,21 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
16351647

16361648
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
16371649
.recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1638-
.round_rate = clk_trion_pll_postdiv_round_rate,
1650+
.determine_rate = clk_trion_pll_postdiv_determine_rate,
16391651
.set_rate = clk_trion_pll_postdiv_set_rate,
16401652
};
16411653
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
16421654

1643-
static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1644-
unsigned long rate, unsigned long *prate)
1655+
static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw,
1656+
struct clk_rate_request *req)
16451657
{
16461658
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
16471659

1648-
return divider_round_rate(hw, rate, prate, pll->post_div_table,
1649-
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1660+
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
1661+
pll->post_div_table,
1662+
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1663+
1664+
return 0;
16501665
}
16511666

16521667
static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
@@ -1681,7 +1696,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
16811696

16821697
const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
16831698
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1684-
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1699+
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
16851700
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
16861701
};
16871702
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
@@ -1833,7 +1848,7 @@ const struct clk_ops clk_alpha_pll_trion_ops = {
18331848
.disable = clk_trion_pll_disable,
18341849
.is_enabled = clk_trion_pll_is_enabled,
18351850
.recalc_rate = clk_trion_pll_recalc_rate,
1836-
.round_rate = clk_alpha_pll_round_rate,
1851+
.determine_rate = clk_alpha_pll_determine_rate,
18371852
.set_rate = alpha_pll_trion_set_rate,
18381853
};
18391854
EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
@@ -1844,14 +1859,14 @@ const struct clk_ops clk_alpha_pll_lucid_ops = {
18441859
.disable = clk_trion_pll_disable,
18451860
.is_enabled = clk_trion_pll_is_enabled,
18461861
.recalc_rate = clk_trion_pll_recalc_rate,
1847-
.round_rate = clk_alpha_pll_round_rate,
1862+
.determine_rate = clk_alpha_pll_determine_rate,
18481863
.set_rate = alpha_pll_trion_set_rate,
18491864
};
18501865
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
18511866

18521867
const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
18531868
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1854-
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1869+
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
18551870
.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
18561871
};
18571872
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
@@ -1903,7 +1918,7 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
19031918
.disable = clk_alpha_pll_disable,
19041919
.is_enabled = clk_alpha_pll_is_enabled,
19051920
.recalc_rate = alpha_pll_fabia_recalc_rate,
1906-
.round_rate = clk_alpha_pll_round_rate,
1921+
.determine_rate = clk_alpha_pll_determine_rate,
19071922
.set_rate = clk_alpha_pll_agera_set_rate,
19081923
};
19091924
EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
@@ -2119,7 +2134,7 @@ const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
21192134
.disable = alpha_pll_lucid_5lpe_disable,
21202135
.is_enabled = clk_trion_pll_is_enabled,
21212136
.recalc_rate = clk_trion_pll_recalc_rate,
2122-
.round_rate = clk_alpha_pll_round_rate,
2137+
.determine_rate = clk_alpha_pll_determine_rate,
21232138
.set_rate = alpha_pll_lucid_5lpe_set_rate,
21242139
};
21252140
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
@@ -2129,13 +2144,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
21292144
.disable = alpha_pll_lucid_5lpe_disable,
21302145
.is_enabled = clk_trion_pll_is_enabled,
21312146
.recalc_rate = clk_trion_pll_recalc_rate,
2132-
.round_rate = clk_alpha_pll_round_rate,
2147+
.determine_rate = clk_alpha_pll_determine_rate,
21332148
};
21342149
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
21352150

21362151
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
21372152
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2138-
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2153+
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
21392154
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
21402155
};
21412156
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
@@ -2304,7 +2319,7 @@ const struct clk_ops clk_alpha_pll_zonda_ops = {
23042319
.disable = clk_zonda_pll_disable,
23052320
.is_enabled = clk_trion_pll_is_enabled,
23062321
.recalc_rate = clk_trion_pll_recalc_rate,
2307-
.round_rate = clk_alpha_pll_round_rate,
2322+
.determine_rate = clk_alpha_pll_determine_rate,
23082323
.set_rate = clk_zonda_pll_set_rate,
23092324
};
23102325
EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
@@ -2529,13 +2544,13 @@ const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
25292544
.disable = alpha_pll_lucid_evo_disable,
25302545
.is_enabled = clk_trion_pll_is_enabled,
25312546
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2532-
.round_rate = clk_alpha_pll_round_rate,
2547+
.determine_rate = clk_alpha_pll_determine_rate,
25332548
};
25342549
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
25352550

25362551
const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
25372552
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2538-
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2553+
.determine_rate = clk_alpha_pll_postdiv_fabia_determine_rate,
25392554
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
25402555
};
25412556
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
@@ -2546,7 +2561,7 @@ const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
25462561
.disable = alpha_pll_lucid_evo_disable,
25472562
.is_enabled = clk_trion_pll_is_enabled,
25482563
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2549-
.round_rate = clk_alpha_pll_round_rate,
2564+
.determine_rate = clk_alpha_pll_determine_rate,
25502565
.set_rate = alpha_pll_lucid_5lpe_set_rate,
25512566
};
25522567
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
@@ -2557,7 +2572,7 @@ const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
25572572
.disable = alpha_pll_reset_lucid_evo_disable,
25582573
.is_enabled = clk_trion_pll_is_enabled,
25592574
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2560-
.round_rate = clk_alpha_pll_round_rate,
2575+
.determine_rate = clk_alpha_pll_determine_rate,
25612576
.set_rate = alpha_pll_lucid_5lpe_set_rate,
25622577
};
25632578
EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
@@ -2732,30 +2747,33 @@ static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
27322747
return parent_rate * l;
27332748
}
27342749

2735-
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2736-
unsigned long *prate)
2750+
static int clk_rivian_evo_pll_determine_rate(struct clk_hw *hw,
2751+
struct clk_rate_request *req)
27372752
{
27382753
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
27392754
unsigned long min_freq, max_freq;
27402755
u32 l;
27412756
u64 a;
27422757

2743-
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2744-
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2745-
return rate;
2758+
req->rate = alpha_pll_round_rate(req->rate, req->best_parent_rate, &l,
2759+
&a, 0);
2760+
if (!pll->vco_table || alpha_pll_find_vco(pll, req->rate))
2761+
return 0;
27462762

27472763
min_freq = pll->vco_table[0].min_freq;
27482764
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
27492765

2750-
return clamp(rate, min_freq, max_freq);
2766+
req->rate = clamp(req->rate, min_freq, max_freq);
2767+
2768+
return 0;
27512769
}
27522770

27532771
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
27542772
.enable = alpha_pll_lucid_5lpe_enable,
27552773
.disable = alpha_pll_lucid_5lpe_disable,
27562774
.is_enabled = clk_trion_pll_is_enabled,
27572775
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
2758-
.round_rate = clk_rivian_evo_pll_round_rate,
2776+
.determine_rate = clk_rivian_evo_pll_determine_rate,
27592777
};
27602778
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
27612779

@@ -2964,7 +2982,7 @@ const struct clk_ops clk_alpha_pll_regera_ops = {
29642982
.disable = clk_zonda_pll_disable,
29652983
.is_enabled = clk_alpha_pll_is_enabled,
29662984
.recalc_rate = clk_trion_pll_recalc_rate,
2967-
.round_rate = clk_alpha_pll_round_rate,
2985+
.determine_rate = clk_alpha_pll_determine_rate,
29682986
.set_rate = clk_zonda_pll_set_rate,
29692987
};
29702988
EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops);
@@ -3169,7 +3187,7 @@ const struct clk_ops clk_alpha_pll_slew_ops = {
31693187
.enable = clk_alpha_pll_slew_enable,
31703188
.disable = clk_alpha_pll_disable,
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.recalc_rate = clk_alpha_pll_recalc_rate,
3172-
.round_rate = clk_alpha_pll_round_rate,
3190+
.determine_rate = clk_alpha_pll_determine_rate,
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.set_rate = clk_alpha_pll_slew_set_rate,
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};
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EXPORT_SYMBOL(clk_alpha_pll_slew_ops);

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