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krishnachaitanya-linuxvinodkoul
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phy: qcom-qmp-pcie: add dual lane PHY support for SM8750
The PCIe Gen3 x2 PHY for SM8750 uses new phy, add the required registers and offsets for this phy. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250809-pakala-v1-2-abf1c416dbaa@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent edafd4f commit 0f05174

3 files changed

Lines changed: 154 additions & 1 deletion

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‎drivers/phy/qualcomm/phy-qcom-qmp-pcie.c‎

Lines changed: 149 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,13 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
9393
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
9494
};
9595

96+
static const unsigned int pciephy_v7_regs_layout[QPHY_LAYOUT_SIZE] = {
97+
[QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,
98+
[QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,
99+
[QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,
100+
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,
101+
};
102+
96103
static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
97104
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
98105
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
@@ -2590,6 +2597,108 @@ static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {
25902597
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
25912598
};
25922599

2600+
static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_serdes_tbl[] = {
2601+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x1),
2602+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
2603+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
2604+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
2605+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
2606+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0x93),
2607+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
2608+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_ENABLE1, 0x90),
2609+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYS_CLK_CTRL, 0x82),
2610+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_IVCO, 0x07),
2611+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
2612+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
2613+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
2614+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
2615+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
2616+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
2617+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x08),
2618+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
2619+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_EN, 0x42),
2620+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x04),
2621+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x0d),
2622+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x0a),
2623+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x1a),
2624+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
2625+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x34),
2626+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0xab),
2627+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0xaa),
2628+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
2629+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
2630+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x55),
2631+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
2632+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x14),
2633+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CLK_SELECT, 0x34),
2634+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
2635+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
2636+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
2637+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC_3, 0x0F),
2638+
QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0xA0),
2639+
};
2640+
2641+
static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_rx_tbl[] = {
2642+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2643+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x11),
2644+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xBF),
2645+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xBF),
2646+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xB7),
2647+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xEA),
2648+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3F),
2649+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x09),
2650+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x49),
2651+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1B),
2652+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x9C),
2653+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xD1),
2654+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH, 0x09),
2655+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH2, 0x49),
2656+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH3, 0x1B),
2657+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_HIGH4, 0x9C),
2658+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_10_LOW, 0xD1),
2659+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1, 0x3E),
2660+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2, 0x1E),
2661+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_TX_ADAPT_POST_THRESH, 0xD2),
2662+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x09),
2663+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x05),
2664+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
2665+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
2666+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x09),
2667+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_ENABLES, 0x1C),
2668+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x60),
2669+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
2670+
QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
2671+
};
2672+
2673+
static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_tx_tbl[] = {
2674+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0x35),
2675+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x10),
2676+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x31),
2677+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x7F),
2678+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x02),
2679+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x08),
2680+
QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x14),
2681+
};
2682+
2683+
static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_tbl[] = {
2684+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x05),
2685+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0x77),
2686+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_RATE_SLEW_CNTRL1, 0x0B),
2687+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG2, 0x0F),
2688+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x8C),
2689+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
2690+
QMP_PHY_INIT_CFG(QPHY_V7_PCS_G3S2_PRE_GAIN, 0x2E),
2691+
};
2692+
2693+
static const struct qmp_phy_init_tbl sm8750_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2694+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1E),
2695+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
2696+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1D),
2697+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2698+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xC1),
2699+
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2700+
};
2701+
25932702
static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
25942703
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
25952704
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -3207,6 +3316,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
32073316
.rx2 = 0x3a00,
32083317
};
32093318

3319+
static const struct qmp_pcie_offsets qmp_pcie_offsets_v7 = {
3320+
.serdes = 0x0,
3321+
.pcs = 0x400,
3322+
.pcs_misc = 0x800,
3323+
.tx = 0x1000,
3324+
.rx = 0x1200,
3325+
.tx2 = 0x1800,
3326+
.rx2 = 0x1a00,
3327+
};
3328+
32103329
static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
32113330
.serdes = 0x1000,
32123331
.pcs = 0x1200,
@@ -3996,6 +4115,33 @@ static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
39964115
.phy_status = PHYSTATUS,
39974116
};
39984117

4118+
static const struct qmp_phy_cfg sm8750_qmp_gen3x2_pciephy_cfg = {
4119+
.lanes = 2,
4120+
4121+
.offsets = &qmp_pcie_offsets_v7,
4122+
4123+
.tbls = {
4124+
.serdes = sm8750_qmp_gen3x2_pcie_serdes_tbl,
4125+
.serdes_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_serdes_tbl),
4126+
.tx = sm8750_qmp_gen3x2_pcie_tx_tbl,
4127+
.tx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_tx_tbl),
4128+
.rx = sm8750_qmp_gen3x2_pcie_rx_tbl,
4129+
.rx_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_rx_tbl),
4130+
.pcs = sm8750_qmp_gen3x2_pcie_pcs_tbl,
4131+
.pcs_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_tbl),
4132+
.pcs_misc = sm8750_qmp_gen3x2_pcie_pcs_misc_tbl,
4133+
.pcs_misc_num = ARRAY_SIZE(sm8750_qmp_gen3x2_pcie_pcs_misc_tbl),
4134+
},
4135+
.reset_list = sdm845_pciephy_reset_l,
4136+
.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
4137+
.vreg_list = qmp_phy_vreg_l,
4138+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
4139+
.regs = pciephy_v7_regs_layout,
4140+
4141+
.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
4142+
.phy_status = PHYSTATUS,
4143+
};
4144+
39994145
static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
40004146
.lanes = 2,
40014147

@@ -5099,6 +5245,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
50995245
}, {
51005246
.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
51015247
.data = &sm8650_qmp_gen4x2_pciephy_cfg,
5248+
}, {
5249+
.compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy",
5250+
.data = &sm8750_qmp_gen3x2_pciephy_cfg,
51025251
}, {
51035252
.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
51045253
.data = &sm8550_qmp_gen3x2_pciephy_cfg,

‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
1818
#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
1919
#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc
20+
#define QPHY_V7_PCS_G12S1_TXDEEMPH_M6DB 0x168
21+
#define QPHY_V7_PCS_G3S2_PRE_GAIN 0x170
2022
#define QPHY_V7_PCS_RX_SIGDET_LVL 0x188
2123
#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
2224
#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194

‎drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v7.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,8 @@
4040
#define QSERDES_V7_RX_UCDR_SB2_GAIN1 0x54
4141
#define QSERDES_V7_RX_UCDR_SB2_GAIN2 0x58
4242
#define QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE 0x60
43+
#define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH1 0xc4
44+
#define QSERDES_V7_RX_TX_ADAPT_PRE_THRESH2 0xc8
4345
#define QSERDES_V7_RX_TX_ADAPT_POST_THRESH 0xcc
4446
#define QSERDES_V7_RX_VGA_CAL_CNTRL1 0xd4
4547
#define QSERDES_V7_RX_VGA_CAL_CNTRL2 0xd8
@@ -50,7 +52,7 @@
5052
#define QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW 0xf8
5153
#define QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH 0xfc
5254
#define QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
53-
#define QSERDES_V7_RX_SIDGET_ENABLES 0x118
55+
#define QSERDES_V7_RX_SIGDET_ENABLES 0x118
5456
#define QSERDES_V7_RX_SIGDET_CNTRL 0x11c
5557
#define QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL 0x124
5658
#define QSERDES_V7_RX_RX_MODE_00_LOW 0x15c

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