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Li Maalexdeucher
Li Ma
authored and
alexdeucher
committed
drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable
Replace IP VERSION with smu->is_apu in if condition. And the dpmtable of smu v14.0.4 is same as smu v14.0.0. Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 9cd2ad1 commit 11382d0

2 files changed

Lines changed: 21 additions & 27 deletions

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‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,7 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
136136
1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
137137

138138
for (i = 0; i < adev->usec_timeout; i++) {
139-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
140-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
139+
if (smu->is_apu)
141140
mp1_fw_flags = RREG32_PCIE(MP1_Public |
142141
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
143142
else
@@ -210,8 +209,7 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
210209
struct amdgpu_device *adev = smu->adev;
211210
uint32_t mp1_fw_flags;
212211

213-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
214-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
212+
if (smu->is_apu)
215213
mp1_fw_flags = RREG32_PCIE(MP1_Public |
216214
(smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
217215
else
@@ -866,8 +864,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
866864
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, 0);
867865

868866
/* For MP1 SW irqs */
869-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
870-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
867+
if (smu->is_apu) {
871868
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
872869
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
873870
WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
@@ -900,8 +897,7 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
900897
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_ENA, val);
901898

902899
/* For MP1 SW irqs */
903-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
904-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
900+
if (smu->is_apu) {
905901
val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
906902
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
907903
val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
@@ -1494,8 +1490,7 @@ int smu_v14_0_set_vcn_enable(struct smu_context *smu,
14941490
if (adev->vcn.harvest_config & (1 << i))
14951491
continue;
14961492

1497-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
1498-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
1493+
if (smu->is_apu) {
14991494
if (i == 0)
15001495
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
15011496
SMU_MSG_PowerUpVcn0 : SMU_MSG_PowerDownVcn0,
@@ -1527,8 +1522,7 @@ int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
15271522
if (adev->jpeg.harvest_config & (1 << i))
15281523
continue;
15291524

1530-
if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
1531-
amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
1525+
if (smu->is_apu) {
15321526
if (i == 0)
15331527
ret = smu_cmn_send_smc_msg_with_param(smu, enable ?
15341528
SMU_MSG_PowerUpJpeg0 : SMU_MSG_PowerDownJpeg0,

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -723,10 +723,10 @@ static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
723723
uint32_t dpm_level,
724724
uint32_t *freq)
725725
{
726-
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
727-
smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
728-
else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
726+
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
729727
smu_v14_0_1_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
728+
else
729+
smu_v14_0_0_get_dpm_freq_by_index(smu, clk_type, dpm_level, freq);
730730

731731
return 0;
732732
}
@@ -999,10 +999,10 @@ static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
999999
uint32_t *min,
10001000
uint32_t *max)
10011001
{
1002-
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1003-
smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1004-
else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1002+
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
10051003
smu_v14_0_1_get_dpm_ultimate_freq(smu, clk_type, min, max);
1004+
else
1005+
smu_v14_0_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
10061006

10071007
return 0;
10081008
}
@@ -1104,10 +1104,10 @@ static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
11041104
enum smu_clk_type clk_type,
11051105
uint32_t *count)
11061106
{
1107-
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1108-
smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
1109-
else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1107+
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
11101108
smu_v14_0_1_get_dpm_level_count(smu, clk_type, count);
1109+
else
1110+
smu_v14_0_0_get_dpm_level_count(smu, clk_type, count);
11111111

11121112
return 0;
11131113
}
@@ -1372,10 +1372,10 @@ static int smu_v14_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *sm
13721372

13731373
static int smu_v14_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
13741374
{
1375-
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1376-
smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);
1377-
else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1375+
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
13781376
smu_v14_0_1_set_fine_grain_gfx_freq_parameters(smu);
1377+
else
1378+
smu_v14_0_0_set_fine_grain_gfx_freq_parameters(smu);
13791379

13801380
return 0;
13811381
}
@@ -1436,10 +1436,10 @@ static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *
14361436

14371437
static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
14381438
{
1439-
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
1440-
smu_14_0_0_get_dpm_table(smu, clock_table);
1441-
else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
1439+
if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
14421440
smu_14_0_1_get_dpm_table(smu, clock_table);
1441+
else
1442+
smu_14_0_0_get_dpm_table(smu, clock_table);
14431443

14441444
return 0;
14451445
}

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