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surajk8surajk8
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drm/i915/ltphy: Program LT Phy Voltage Swing
Program LT Phy voltage swing using the Swing tables and plug in the function at encoder->set_signal_level Bspec: 74493 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com
1 parent c4b2da6 commit 13ba213

4 files changed

Lines changed: 88 additions & 3 deletions

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‎drivers/gpu/drm/i915/display/intel_ddi.c‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1467,10 +1467,15 @@ static int translate_signal_level(struct intel_dp *intel_dp,
14671467
u8 signal_levels)
14681468
{
14691469
struct intel_display *display = to_intel_display(intel_dp);
1470+
const u8 *signal_array;
1471+
size_t array_size;
14701472
int i;
14711473

1472-
for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1473-
if (index_to_dp_signal_levels[i] == signal_levels)
1474+
signal_array = index_to_dp_signal_levels;
1475+
array_size = ARRAY_SIZE(index_to_dp_signal_levels);
1476+
1477+
for (i = 0; i < array_size; i++) {
1478+
if (signal_array[i] == signal_levels)
14741479
return i;
14751480
}
14761481

@@ -5301,7 +5306,9 @@ void intel_ddi_init(struct intel_display *display,
53015306
encoder->get_config = hsw_ddi_get_config;
53025307
}
53035308

5304-
if (DISPLAY_VER(display) >= 14) {
5309+
if (HAS_LT_PHY(display)) {
5310+
encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
5311+
} else if (DISPLAY_VER(display) >= 14) {
53055312
encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
53065313
} else if (display->platform.dg2) {
53075314
encoder->set_signal_levels = intel_snps_phy_set_signal_levels;

‎drivers/gpu/drm/i915/display/intel_lt_phy.c‎

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,8 @@
99
#include "i915_utils.h"
1010
#include "intel_cx0_phy.h"
1111
#include "intel_cx0_phy_regs.h"
12+
#include "intel_ddi.h"
13+
#include "intel_ddi_buf_trans.h"
1214
#include "intel_de.h"
1315
#include "intel_display.h"
1416
#include "intel_display_types.h"
@@ -1003,6 +1005,12 @@ static void intel_lt_phy_write(struct intel_encoder *encoder,
10031005
intel_cx0_write(encoder, lane_mask, addr, data, committed);
10041006
}
10051007

1008+
static void intel_lt_phy_rmw(struct intel_encoder *encoder,
1009+
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
1010+
{
1011+
intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed);
1012+
}
1013+
10061014
static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder,
10071015
int lane)
10081016
{
@@ -1706,6 +1714,61 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
17061714
intel_lt_phy_transaction_end(encoder, wakeref);
17071715
}
17081716

1717+
void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
1718+
const struct intel_crtc_state *crtc_state)
1719+
{
1720+
struct intel_display *display = to_intel_display(encoder);
1721+
const struct intel_ddi_buf_trans *trans;
1722+
u8 owned_lane_mask;
1723+
intel_wakeref_t wakeref;
1724+
int n_entries, ln;
1725+
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1726+
1727+
if (intel_tc_port_in_tbt_alt_mode(dig_port))
1728+
return;
1729+
1730+
owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
1731+
1732+
wakeref = intel_lt_phy_transaction_begin(encoder);
1733+
1734+
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1735+
if (drm_WARN_ON_ONCE(display->drm, !trans)) {
1736+
intel_lt_phy_transaction_end(encoder, wakeref);
1737+
return;
1738+
}
1739+
1740+
for (ln = 0; ln < crtc_state->lane_count; ln++) {
1741+
int level = intel_ddi_level(encoder, crtc_state, ln);
1742+
int lane = ln / 2;
1743+
int tx = ln % 2;
1744+
u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
1745+
1746+
if (!(lane_mask & owned_lane_mask))
1747+
continue;
1748+
1749+
intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx),
1750+
LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK,
1751+
LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) |
1752+
LT_PHY_TX_SWING(trans->entries[level].lt.txswing),
1753+
MB_WRITE_COMMITTED);
1754+
1755+
intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx),
1756+
LT_PHY_TX_CURSOR_MASK,
1757+
LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor),
1758+
MB_WRITE_COMMITTED);
1759+
intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx),
1760+
LT_PHY_TX_CURSOR_MASK,
1761+
LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor),
1762+
MB_WRITE_COMMITTED);
1763+
intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx),
1764+
LT_PHY_TX_CURSOR_MASK,
1765+
LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor),
1766+
MB_WRITE_COMMITTED);
1767+
}
1768+
1769+
intel_lt_phy_transaction_end(encoder, wakeref);
1770+
}
1771+
17091772
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
17101773
const struct intel_crtc_state *crtc_state)
17111774
{

‎drivers/gpu/drm/i915/display/intel_lt_phy.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
2020
struct intel_encoder *encoder);
2121
int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
2222
const struct intel_crtc_state *crtc_state);
23+
void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
24+
const struct intel_crtc_state *crtc_state);
2325
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
2426
const struct intel_crtc_state *crtc_state);
2527
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);

‎drivers/gpu/drm/i915/display/intel_lt_phy_regs.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,19 @@
1919
#define LT_PHY_MAC_VDR _MMIO(0xC00)
2020
#define LT_PHY_PCLKIN_GATE REG_BIT8(0)
2121

22+
/* LT Phy Pipe Spec Registers */
23+
#define LT_PHY_TXY_CTL8(idx) (0x408 + (0x200 * (idx)))
24+
#define LT_PHY_TX_SWING_LEVEL_MASK REG_GENMASK8(7, 4)
25+
#define LT_PHY_TX_SWING_LEVEL(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_LEVEL_MASK, val)
26+
#define LT_PHY_TX_SWING_MASK REG_BIT8(3)
27+
#define LT_PHY_TX_SWING(val) REG_FIELD_PREP8(LT_PHY_TX_SWING_MASK, val)
28+
29+
#define LT_PHY_TXY_CTL2(idx) (0x402 + (0x200 * (idx)))
30+
#define LT_PHY_TXY_CTL3(idx) (0x403 + (0x200 * (idx)))
31+
#define LT_PHY_TXY_CTL4(idx) (0x404 + (0x200 * (idx)))
32+
#define LT_PHY_TX_CURSOR_MASK REG_GENMASK8(5, 0)
33+
#define LT_PHY_TX_CURSOR(val) REG_FIELD_PREP8(LT_PHY_TX_CURSOR_MASK, val)
34+
2235
/* LT Phy Vendor Register */
2336
#define LT_PHY_VDR_0_CONFIG 0xC02
2437
#define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)

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