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Cruise Hungalexdeucher
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drm/amd/display: Remove unused tunnel BW validation
[Why & How] The tunnel BW validation code has changed to the new one. Remove the unused code. The DP tunneling overhead is not updated in SST. Move updating DP tunneling overhead for both SST and MST. Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 158b920 commit 156374b

9 files changed

Lines changed: 19 additions & 224 deletions

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drivers/gpu/drm/amd/display/dc/core/dc_link_exports.c

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -515,11 +515,6 @@ void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
515515
link->dc->link_srv->enable_hpd_filter(link, enable);
516516
}
517517

518-
bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, const unsigned int count)
519-
{
520-
return dc->link_srv->validate_dpia_bandwidth(streams, count);
521-
}
522-
523518
enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx)
524519
{
525520
return dc->link_srv->validate_dp_tunnel_bandwidth(dc, new_ctx);

drivers/gpu/drm/amd/display/dc/dc.h

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2416,19 +2416,6 @@ void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
24162416
void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
24172417
struct dc_link *link, int peak_bw);
24182418

2419-
/*
2420-
* Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2421-
* available BW for each host router
2422-
*
2423-
* @dc: pointer to dc struct
2424-
* @stream: pointer to all possible streams
2425-
* @count: number of valid DPIA streams
2426-
*
2427-
* return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2428-
*/
2429-
bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2430-
const unsigned int count);
2431-
24322419
/*
24332420
* Calculates the DP tunneling bandwidth required for the stream timing
24342421
* and aggregates the stream bandwidth for the respective DP tunneling link

drivers/gpu/drm/amd/display/dc/inc/link.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,9 +144,6 @@ struct link_service {
144144
uint32_t (*dp_link_bandwidth_kbps)(
145145
const struct dc_link *link,
146146
const struct dc_link_settings *link_settings);
147-
bool (*validate_dpia_bandwidth)(
148-
const struct dc_stream_state *stream,
149-
const unsigned int num_streams);
150147
enum dc_status (*validate_dp_tunnel_bandwidth)(
151148
const struct dc *dc,
152149
const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2295,10 +2295,11 @@ static bool allocate_usb4_bandwidth_for_stream(struct dc_stream_state *stream, i
22952295
}
22962296

22972297
link->dpia_bw_alloc_config.remote_sink_req_bw[sink_index] = bw;
2298-
link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_mst_overhead(link);
2299-
req_bw += link->dpia_bw_alloc_config.dp_overhead;
23002298
}
23012299

2300+
link->dpia_bw_alloc_config.dp_overhead = link_dpia_get_dp_overhead(link);
2301+
req_bw += link->dpia_bw_alloc_config.dp_overhead;
2302+
23022303
link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, req_bw);
23032304

23042305
if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {

drivers/gpu/drm/amd/display/dc/link/link_factory.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,6 @@ static void construct_link_service_validation(struct link_service *link_srv)
100100
{
101101
link_srv->validate_mode_timing = link_validate_mode_timing;
102102
link_srv->dp_link_bandwidth_kbps = dp_link_bandwidth_kbps;
103-
link_srv->validate_dpia_bandwidth = link_validate_dpia_bandwidth;
104103
link_srv->validate_dp_tunnel_bandwidth = link_validate_dp_tunnel_bandwidth;
105104
link_srv->dp_required_hblank_size_bytes = dp_required_hblank_size_bytes;
106105
}

drivers/gpu/drm/amd/display/dc/link/link_validation.c

Lines changed: 2 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -367,65 +367,6 @@ enum dc_status link_validate_mode_timing(
367367
return DC_OK;
368368
}
369369

370-
/*
371-
* This function calculates the bandwidth required for the stream timing
372-
* and aggregates the stream bandwidth for the respective dpia link
373-
*
374-
* @stream: pointer to the dc_stream_state struct instance
375-
* @num_streams: number of streams to be validated
376-
*
377-
* return: true if validation is succeeded
378-
*/
379-
bool link_validate_dpia_bandwidth(const struct dc_stream_state *stream, const unsigned int num_streams)
380-
{
381-
int bw_needed[MAX_DPIA_NUM] = {0};
382-
struct dc_link *dpia_link[MAX_DPIA_NUM] = {0};
383-
int num_dpias = 0;
384-
385-
for (unsigned int i = 0; i < num_streams; ++i) {
386-
if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT) {
387-
/* new dpia sst stream, check whether it exceeds max dpia */
388-
if (num_dpias >= MAX_DPIA_NUM)
389-
return false;
390-
391-
dpia_link[num_dpias] = stream[i].link;
392-
bw_needed[num_dpias] = dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
393-
dc_link_get_highest_encoding_format(dpia_link[num_dpias]));
394-
num_dpias++;
395-
} else if (stream[i].signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
396-
uint8_t j = 0;
397-
/* check whether its a known dpia link */
398-
for (; j < num_dpias; ++j) {
399-
if (dpia_link[j] == stream[i].link)
400-
break;
401-
}
402-
403-
if (j == num_dpias) {
404-
/* new dpia mst stream, check whether it exceeds max dpia */
405-
if (num_dpias >= MAX_DPIA_NUM)
406-
return false;
407-
else {
408-
dpia_link[j] = stream[i].link;
409-
num_dpias++;
410-
}
411-
}
412-
413-
bw_needed[j] += dc_bandwidth_in_kbps_from_timing(&stream[i].timing,
414-
dc_link_get_highest_encoding_format(dpia_link[j]));
415-
}
416-
}
417-
418-
/* Include dp overheads */
419-
for (uint8_t i = 0; i < num_dpias; ++i) {
420-
int dp_overhead = 0;
421-
422-
dp_overhead = link_dpia_get_dp_mst_overhead(dpia_link[i]);
423-
bw_needed[i] += dp_overhead;
424-
}
425-
426-
return dpia_validate_usb4_bw(dpia_link, bw_needed, num_dpias);
427-
}
428-
429370
static const struct dc_tunnel_settings *get_dp_tunnel_settings(const struct dc_state *context,
430371
const struct dc_stream_state *stream)
431372
{
@@ -454,6 +395,7 @@ enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const stru
454395
uint8_t link_count = 0;
455396
enum dc_status result = DC_OK;
456397

398+
// Iterate through streams in the new context
457399
for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) {
458400
const struct dc_stream_state *stream = new_ctx->streams[i];
459401
const struct dc_link *link;
@@ -477,6 +419,7 @@ enum dc_status link_validate_dp_tunnel_bandwidth(const struct dc *dc, const stru
477419

478420
timing_bw = dp_get_timing_bandwidth_kbps(&stream->timing, link);
479421

422+
// Find an existing entry for this 'link' in 'dpia_link_sets'
480423
for (uint8_t j = 0; j < MAX_DPIA_NUM; j++) {
481424
bool is_new_slot = false;
482425

drivers/gpu/drm/amd/display/dc/link/link_validation.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,6 @@ enum dc_status link_validate_mode_timing(
3030
const struct dc_stream_state *stream,
3131
struct dc_link *link,
3232
const struct dc_crtc_timing *timing);
33-
bool link_validate_dpia_bandwidth(
34-
const struct dc_stream_state *stream,
35-
const unsigned int num_streams);
3633
enum dc_status link_validate_dp_tunnel_bandwidth(
3734
const struct dc *dc,
3835
const struct dc_state *new_ctx);

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c

Lines changed: 13 additions & 125 deletions
Original file line numberDiff line numberDiff line change
@@ -162,78 +162,6 @@ static void retrieve_usb4_dp_bw_allocation_info(struct dc_link *link)
162162
link->dpia_bw_alloc_config.nrd_max_lane_count);
163163
}
164164

165-
static uint8_t get_lowest_dpia_index(struct dc_link *link)
166-
{
167-
const struct dc *dc_struct = link->dc;
168-
uint8_t idx = 0xFF;
169-
int i;
170-
171-
for (i = 0; i < MAX_LINKS; ++i) {
172-
173-
if (!dc_struct->links[i] ||
174-
dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
175-
continue;
176-
177-
if (idx > dc_struct->links[i]->link_index) {
178-
idx = dc_struct->links[i]->link_index;
179-
break;
180-
}
181-
}
182-
183-
return idx;
184-
}
185-
186-
/*
187-
* Get the maximum dp tunnel banwidth of host router
188-
*
189-
* @dc: pointer to the dc struct instance
190-
* @hr_index: host router index
191-
*
192-
* return: host router maximum dp tunnel bandwidth
193-
*/
194-
static int get_host_router_total_dp_tunnel_bw(const struct dc *dc, uint8_t hr_index)
195-
{
196-
uint8_t lowest_dpia_index = get_lowest_dpia_index(dc->links[0]);
197-
uint8_t hr_index_temp = 0;
198-
struct dc_link *link_dpia_primary, *link_dpia_secondary;
199-
int total_bw = 0;
200-
201-
for (uint8_t i = 0; i < MAX_LINKS - 1; ++i) {
202-
203-
if (!dc->links[i] || dc->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
204-
continue;
205-
206-
hr_index_temp = (dc->links[i]->link_index - lowest_dpia_index) / 2;
207-
208-
if (hr_index_temp == hr_index) {
209-
link_dpia_primary = dc->links[i];
210-
link_dpia_secondary = dc->links[i + 1];
211-
212-
/**
213-
* If BW allocation enabled on both DPIAs, then
214-
* HR BW = Estimated(dpia_primary) + Allocated(dpia_secondary)
215-
* otherwise HR BW = Estimated(bw alloc enabled dpia)
216-
*/
217-
if ((link_dpia_primary->hpd_status &&
218-
link_dpia_primary->dpia_bw_alloc_config.bw_alloc_enabled) &&
219-
(link_dpia_secondary->hpd_status &&
220-
link_dpia_secondary->dpia_bw_alloc_config.bw_alloc_enabled)) {
221-
total_bw += link_dpia_primary->dpia_bw_alloc_config.estimated_bw +
222-
link_dpia_secondary->dpia_bw_alloc_config.allocated_bw;
223-
} else if (link_dpia_primary->hpd_status &&
224-
link_dpia_primary->dpia_bw_alloc_config.bw_alloc_enabled) {
225-
total_bw = link_dpia_primary->dpia_bw_alloc_config.estimated_bw;
226-
} else if (link_dpia_secondary->hpd_status &&
227-
link_dpia_secondary->dpia_bw_alloc_config.bw_alloc_enabled) {
228-
total_bw += link_dpia_secondary->dpia_bw_alloc_config.estimated_bw;
229-
}
230-
break;
231-
}
232-
}
233-
234-
return total_bw;
235-
}
236-
237165
/*
238166
* Cleanup function for when the dpia is unplugged to reset struct
239167
* and perform any required clean up
@@ -398,54 +326,9 @@ void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int r
398326
DC_LOG_DEBUG("%s: BW Allocation mode not available", __func__);
399327
}
400328

401-
bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed_per_dpia, const unsigned int num_dpias)
402-
{
403-
bool ret = true;
404-
int bw_needed_per_hr[MAX_HOST_ROUTERS_NUM] = { 0 };
405-
int host_router_total_dp_bw = 0;
406-
uint8_t lowest_dpia_index, i, hr_index;
407-
408-
if (!num_dpias || num_dpias > MAX_DPIA_NUM)
409-
return ret;
410-
411-
lowest_dpia_index = get_lowest_dpia_index(link[0]);
412-
413-
/* get total Host Router BW with granularity for the given modes */
414-
for (i = 0; i < num_dpias; ++i) {
415-
int granularity_Gbps = 0;
416-
int bw_granularity = 0;
417-
418-
if (!link[i]->dpia_bw_alloc_config.bw_alloc_enabled)
419-
continue;
420-
421-
if (link[i]->link_index < lowest_dpia_index)
422-
continue;
423-
424-
granularity_Gbps = (Kbps_TO_Gbps / link[i]->dpia_bw_alloc_config.bw_granularity);
425-
bw_granularity = (bw_needed_per_dpia[i] / granularity_Gbps) * granularity_Gbps +
426-
((bw_needed_per_dpia[i] % granularity_Gbps) ? granularity_Gbps : 0);
427-
428-
hr_index = (link[i]->link_index - lowest_dpia_index) / 2;
429-
bw_needed_per_hr[hr_index] += bw_granularity;
430-
}
431-
432-
/* validate against each Host Router max BW */
433-
for (hr_index = 0; hr_index < MAX_HOST_ROUTERS_NUM; ++hr_index) {
434-
if (bw_needed_per_hr[hr_index]) {
435-
host_router_total_dp_bw = get_host_router_total_dp_tunnel_bw(link[0]->dc, hr_index);
436-
if (bw_needed_per_hr[hr_index] > host_router_total_dp_bw) {
437-
ret = false;
438-
break;
439-
}
440-
}
441-
}
442-
443-
return ret;
444-
}
445-
446-
uint32_t link_dpia_get_dp_mst_overhead(const struct dc_link *link)
329+
uint32_t link_dpia_get_dp_overhead(const struct dc_link *link)
447330
{
448-
uint32_t link_mst_overhead = 0;
331+
uint32_t link_dp_overhead = 0;
449332

450333
if ((link->type == dc_connection_mst_branch) &&
451334
!link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
@@ -458,12 +341,12 @@ uint32_t link_dpia_get_dp_mst_overhead(const struct dc_link *link)
458341
uint32_t link_bw_in_kbps = (uint32_t)link_cap->link_rate *
459342
(uint32_t)link_cap->lane_count *
460343
LINK_RATE_REF_FREQ_IN_KHZ * 8;
461-
link_mst_overhead = (link_bw_in_kbps / MST_TIME_SLOT_COUNT)
344+
link_dp_overhead = (link_bw_in_kbps / MST_TIME_SLOT_COUNT)
462345
+ ((link_bw_in_kbps % MST_TIME_SLOT_COUNT) ? 1 : 0);
463346
}
464347
}
465348

466-
return link_mst_overhead;
349+
return link_dp_overhead;
467350
}
468351

469352
/*
@@ -484,11 +367,13 @@ bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set
484367
struct usb4_router_validation_set router_sets[MAX_HOST_ROUTERS_NUM] = { 0 };
485368
uint8_t i;
486369
bool is_success = true;
487-
uint8_t rounter_count = 0;
370+
uint8_t router_count = 0;
488371

489372
if ((dpia_link_sets == NULL) || (count == 0))
490373
return is_success;
491374

375+
// Iterate through each DP tunneling link (DPIA).
376+
// Aggregate its bandwidth requirements onto the respective USB4 router.
492377
for (i = 0; i < count; i++) {
493378
link = dpia_link_sets[i].link;
494379
link_required_bw = dpia_link_sets[i].required_bw;
@@ -498,17 +383,18 @@ bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set
498383
break;
499384

500385
if (link->type == dc_connection_mst_branch)
501-
link_required_bw += link_dpia_get_dp_mst_overhead(link);
386+
link_required_bw += link_dpia_get_dp_overhead(link);
502387

503388
granularity_Gbps = (Kbps_TO_Gbps / dp_tunnel_settings->bw_granularity);
504389
link_bw_granularity = (link_required_bw / granularity_Gbps) * granularity_Gbps +
505390
((link_required_bw % granularity_Gbps) ? granularity_Gbps : 0);
506391

392+
// Find or add the USB4 router associated with the current DPIA link
507393
for (uint8_t j = 0; j < MAX_HOST_ROUTERS_NUM; j++) {
508394
if (router_sets[j].is_valid == false) {
509395
router_sets[j].is_valid = true;
510396
router_sets[j].cm_id = dp_tunnel_settings->cm_id;
511-
rounter_count++;
397+
router_count++;
512398
}
513399

514400
if (router_sets[j].cm_id == dp_tunnel_settings->cm_id) {
@@ -531,12 +417,14 @@ bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set
531417
}
532418
}
533419

534-
for (i = 0; i < rounter_count; i++) {
420+
// Validate bandwidth for each unique router found.
421+
for (i = 0; i < router_count; i++) {
535422
uint32_t total_bw = 0;
536423

537424
if (router_sets[i].is_valid == false)
538425
break;
539426

427+
// Determine the total available bandwidth for the current router based on aggregated data
540428
if ((router_sets[i].dpia_count == 1) || (router_sets[i].allocated_bw == 0))
541429
total_bw = router_sets[i].estimated_bw;
542430
else

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.h

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -79,26 +79,14 @@ void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int r
7979
*/
8080
void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw);
8181

82-
/*
83-
* Handle the validation of total BW here and confirm that the bw used by each
84-
* DPIA doesn't exceed available BW for each host router (HR)
85-
*
86-
* @link[]: array of link pointer to all possible DPIA links
87-
* @bw_needed[]: bw needed for each DPIA link based on timing
88-
* @num_dpias: Number of DPIAs for the above 2 arrays. Should always be <= MAX_DPIA_NUM
89-
*
90-
* return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
91-
*/
92-
bool dpia_validate_usb4_bw(struct dc_link **link, int *bw_needed, const unsigned int num_dpias);
93-
9482
/*
9583
* Obtain all the DP overheads in dp tunneling for the dpia link
9684
*
9785
* @link: pointer to the dc_link struct instance
9886
*
9987
* return: DP overheads in DP tunneling
10088
*/
101-
uint32_t link_dpia_get_dp_mst_overhead(const struct dc_link *link);
89+
uint32_t link_dpia_get_dp_overhead(const struct dc_link *link);
10290

10391
/*
10492
* Handle DP BW allocation status register

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