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Jie GanSuzuki K Poulose
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dt-bindings: arm: Add Coresight TMC Control Unit hardware
Add binding file to specify how to define a Coresight TMC Control Unit device in device tree. It is responsible for controlling the data filter function based on the source device's Trace ID for TMC ETR device. The trace data with that Trace id can get into ETR's buffer while other trace data gets ignored. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jie Gan <quic_jiegan@quicinc.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/20250303032931.2500935-9-quic_jiegan@quicinc.com
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CoreSight TMC Control Unit
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maintainers:
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- Yuanfang Zhang <quic_yuanfang@quicinc.com>
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- Mao Jinlong <quic_jinlmao@quicinc.com>
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- Jie Gan <quic_jiegan@quicinc.com>
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description: |
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The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
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Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations.
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The configuration mode (ETB, ETF, ETR) is discovered at boot time when
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the device is probed.
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The Coresight TMC Control unit controls various Coresight behaviors.
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It works as a helper device when connected to TMC ETR device.
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It is responsible for controlling the data filter function based on
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the source device's Trace ID for TMC ETR device. The trace data with
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that Trace id can get into ETR's buffer while other trace data gets
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ignored.
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properties:
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compatible:
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enum:
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- qcom,sa8775p-ctcu
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: apb
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in-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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patternProperties:
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'^port(@[0-1])?$':
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description: Input connections from CoreSight Trace bus
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$ref: /schemas/graph.yaml#/properties/port
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required:
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- compatible
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- reg
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- in-ports
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additionalProperties: false
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examples:
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- |
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ctcu@1001000 {
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compatible = "qcom,sa8775p-ctcu";
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reg = <0x1001000 0x1000>;
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clocks = <&aoss_qmp>;
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clock-names = "apb";
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ctcu_in_port0: endpoint {
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remote-endpoint = <&etr0_out_port>;
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};
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};
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port@1 {
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reg = <1>;
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ctcu_in_port1: endpoint {
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remote-endpoint = <&etr1_out_port>;
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};
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};
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};
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};

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