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james-c-linarobroonie
james-c-linaro
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broonie
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spi: spi-fsl-dspi: Define regmaps per device
Refactor the regmaps so they can be defined per device rather than programmatically. This will allow us to add two new regmaps for S32G in a later commit. No functional changes. Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-5-bea884630cfb@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
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Lines changed: 74 additions & 62 deletions

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‎drivers/spi/spi-fsl-dspi.c‎

Lines changed: 74 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ struct fsl_dspi_devtype_data {
122122
enum dspi_trans_mode trans_mode;
123123
u8 max_clock_factor;
124124
int fifo_size;
125+
const struct regmap_config *regmap;
125126
};
126127

127128
enum {
@@ -137,60 +138,130 @@ enum {
137138
VF610,
138139
};
139140

141+
static const struct regmap_range dspi_yes_ranges[] = {
142+
regmap_reg_range(SPI_MCR, SPI_MCR),
143+
regmap_reg_range(SPI_TCR, SPI_CTAR(3)),
144+
regmap_reg_range(SPI_SR, SPI_TXFR3),
145+
regmap_reg_range(SPI_RXFR0, SPI_RXFR3),
146+
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),
147+
regmap_reg_range(SPI_SREX, SPI_SREX),
148+
};
149+
150+
static const struct regmap_access_table dspi_access_table = {
151+
.yes_ranges = dspi_yes_ranges,
152+
.n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges),
153+
};
154+
155+
static const struct regmap_range dspi_volatile_ranges[] = {
156+
regmap_reg_range(SPI_MCR, SPI_TCR),
157+
regmap_reg_range(SPI_SR, SPI_SR),
158+
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
159+
regmap_reg_range(SPI_SREX, SPI_SREX),
160+
};
161+
162+
static const struct regmap_access_table dspi_volatile_table = {
163+
.yes_ranges = dspi_volatile_ranges,
164+
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
165+
};
166+
167+
enum {
168+
DSPI_REGMAP,
169+
DSPI_XSPI_REGMAP,
170+
DSPI_PUSHR,
171+
};
172+
173+
static const struct regmap_config dspi_regmap_config[] = {
174+
[DSPI_REGMAP] = {
175+
.reg_bits = 32,
176+
.val_bits = 32,
177+
.reg_stride = 4,
178+
.max_register = SPI_RXFR3,
179+
.volatile_table = &dspi_volatile_table,
180+
.rd_table = &dspi_access_table,
181+
.wr_table = &dspi_access_table,
182+
},
183+
[DSPI_XSPI_REGMAP] = {
184+
.reg_bits = 32,
185+
.val_bits = 32,
186+
.reg_stride = 4,
187+
.max_register = SPI_SREX,
188+
.volatile_table = &dspi_volatile_table,
189+
.rd_table = &dspi_access_table,
190+
.wr_table = &dspi_access_table,
191+
},
192+
[DSPI_PUSHR] = {
193+
.name = "pushr",
194+
.reg_bits = 16,
195+
.val_bits = 16,
196+
.reg_stride = 2,
197+
.max_register = 0x2,
198+
},
199+
};
200+
140201
static const struct fsl_dspi_devtype_data devtype_data[] = {
141202
[VF610] = {
142203
.trans_mode = DSPI_DMA_MODE,
143204
.max_clock_factor = 2,
144205
.fifo_size = 4,
206+
.regmap = &dspi_regmap_config[DSPI_REGMAP],
145207
},
146208
[LS1021A] = {
147209
/* Has A-011218 DMA erratum */
148210
.trans_mode = DSPI_XSPI_MODE,
149211
.max_clock_factor = 8,
150212
.fifo_size = 4,
213+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
151214
},
152215
[LS1012A] = {
153216
/* Has A-011218 DMA erratum */
154217
.trans_mode = DSPI_XSPI_MODE,
155218
.max_clock_factor = 8,
156219
.fifo_size = 16,
220+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
157221
},
158222
[LS1028A] = {
159223
.trans_mode = DSPI_XSPI_MODE,
160224
.max_clock_factor = 8,
161225
.fifo_size = 4,
226+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
162227
},
163228
[LS1043A] = {
164229
/* Has A-011218 DMA erratum */
165230
.trans_mode = DSPI_XSPI_MODE,
166231
.max_clock_factor = 8,
167232
.fifo_size = 16,
233+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
168234
},
169235
[LS1046A] = {
170236
/* Has A-011218 DMA erratum */
171237
.trans_mode = DSPI_XSPI_MODE,
172238
.max_clock_factor = 8,
173239
.fifo_size = 16,
240+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
174241
},
175242
[LS2080A] = {
176243
.trans_mode = DSPI_XSPI_MODE,
177244
.max_clock_factor = 8,
178245
.fifo_size = 4,
246+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
179247
},
180248
[LS2085A] = {
181249
.trans_mode = DSPI_XSPI_MODE,
182250
.max_clock_factor = 8,
183251
.fifo_size = 4,
252+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
184253
},
185254
[LX2160A] = {
186255
.trans_mode = DSPI_XSPI_MODE,
187256
.max_clock_factor = 8,
188257
.fifo_size = 4,
258+
.regmap = &dspi_regmap_config[DSPI_XSPI_REGMAP],
189259
},
190260
[MCF5441X] = {
191261
.trans_mode = DSPI_DMA_MODE,
192262
.max_clock_factor = 8,
193263
.fifo_size = 16,
264+
.regmap = &dspi_regmap_config[DSPI_REGMAP],
194265
},
195266
};
196267

@@ -1191,61 +1262,6 @@ static int dspi_resume(struct device *dev)
11911262

11921263
static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
11931264

1194-
static const struct regmap_range dspi_yes_ranges[] = {
1195-
regmap_reg_range(SPI_MCR, SPI_MCR),
1196-
regmap_reg_range(SPI_TCR, SPI_CTAR(3)),
1197-
regmap_reg_range(SPI_SR, SPI_TXFR3),
1198-
regmap_reg_range(SPI_RXFR0, SPI_RXFR3),
1199-
regmap_reg_range(SPI_CTARE(0), SPI_CTARE(3)),
1200-
regmap_reg_range(SPI_SREX, SPI_SREX),
1201-
};
1202-
1203-
static const struct regmap_access_table dspi_access_table = {
1204-
.yes_ranges = dspi_yes_ranges,
1205-
.n_yes_ranges = ARRAY_SIZE(dspi_yes_ranges),
1206-
};
1207-
1208-
static const struct regmap_range dspi_volatile_ranges[] = {
1209-
regmap_reg_range(SPI_MCR, SPI_TCR),
1210-
regmap_reg_range(SPI_SR, SPI_SR),
1211-
regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1212-
regmap_reg_range(SPI_SREX, SPI_SREX),
1213-
};
1214-
1215-
static const struct regmap_access_table dspi_volatile_table = {
1216-
.yes_ranges = dspi_volatile_ranges,
1217-
.n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1218-
};
1219-
1220-
static const struct regmap_config dspi_regmap_config = {
1221-
.reg_bits = 32,
1222-
.val_bits = 32,
1223-
.reg_stride = 4,
1224-
.max_register = SPI_RXFR3,
1225-
.volatile_table = &dspi_volatile_table,
1226-
.rd_table = &dspi_access_table,
1227-
.wr_table = &dspi_access_table,
1228-
};
1229-
1230-
static const struct regmap_config dspi_xspi_regmap_config[] = {
1231-
{
1232-
.reg_bits = 32,
1233-
.val_bits = 32,
1234-
.reg_stride = 4,
1235-
.max_register = SPI_SREX,
1236-
.volatile_table = &dspi_volatile_table,
1237-
.rd_table = &dspi_access_table,
1238-
.wr_table = &dspi_access_table,
1239-
},
1240-
{
1241-
.name = "pushr",
1242-
.reg_bits = 16,
1243-
.val_bits = 16,
1244-
.reg_stride = 2,
1245-
.max_register = 0x2,
1246-
},
1247-
};
1248-
12491265
static int dspi_init(struct fsl_dspi *dspi)
12501266
{
12511267
unsigned int mcr;
@@ -1305,7 +1321,6 @@ static int dspi_target_abort(struct spi_controller *host)
13051321
static int dspi_probe(struct platform_device *pdev)
13061322
{
13071323
struct device_node *np = pdev->dev.of_node;
1308-
const struct regmap_config *regmap_config;
13091324
struct fsl_dspi_platform_data *pdata;
13101325
struct spi_controller *ctlr;
13111326
int ret, cs_num, bus_num = -1;
@@ -1388,11 +1403,8 @@ static int dspi_probe(struct platform_device *pdev)
13881403
goto out_ctlr_put;
13891404
}
13901405

1391-
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1392-
regmap_config = &dspi_xspi_regmap_config[0];
1393-
else
1394-
regmap_config = &dspi_regmap_config;
1395-
dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1406+
dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1407+
dspi->devtype_data->regmap);
13961408
if (IS_ERR(dspi->regmap)) {
13971409
dev_err(&pdev->dev, "failed to init regmap: %ld\n",
13981410
PTR_ERR(dspi->regmap));
@@ -1403,7 +1415,7 @@ static int dspi_probe(struct platform_device *pdev)
14031415
if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
14041416
dspi->regmap_pushr = devm_regmap_init_mmio(
14051417
&pdev->dev, base + SPI_PUSHR,
1406-
&dspi_xspi_regmap_config[1]);
1418+
&dspi_regmap_config[DSPI_PUSHR]);
14071419
if (IS_ERR(dspi->regmap_pushr)) {
14081420
dev_err(&pdev->dev,
14091421
"failed to init pushr regmap: %ld\n",

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