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marcanjannau
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ASoC: tas2764: Set the SDOUT polarity correctly
TX launch polarity needs to be the opposite of RX capture polarity, to generate the right bit slot alignment. Signed-off-by: Hector Martin <marcan@marcan.st>
1 parent d62e251 commit 16c38ff

2 files changed

Lines changed: 15 additions & 1 deletion

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sound/soc/codecs/tas2764.c

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -407,7 +407,7 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
407407
{
408408
struct snd_soc_component *component = dai->component;
409409
struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
410-
u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0;
410+
u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0, asi_cfg_4 = 0;
411411
int ret;
412412

413413
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -416,12 +416,14 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
416416
fallthrough;
417417
case SND_SOC_DAIFMT_NB_NF:
418418
asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING;
419+
asi_cfg_4 = TAS2764_TDM_CFG4_TX_FALLING;
419420
break;
420421
case SND_SOC_DAIFMT_IB_IF:
421422
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
422423
fallthrough;
423424
case SND_SOC_DAIFMT_IB_NF:
424425
asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING;
426+
asi_cfg_4 = TAS2764_TDM_CFG4_TX_RISING;
425427
break;
426428
}
427429

@@ -431,6 +433,12 @@ static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
431433
if (ret < 0)
432434
return ret;
433435

436+
ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG4,
437+
TAS2764_TDM_CFG4_TX_MASK,
438+
asi_cfg_4);
439+
if (ret < 0)
440+
return ret;
441+
434442
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
435443
case SND_SOC_DAIFMT_I2S:
436444
asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;

sound/soc/codecs/tas2764.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,12 @@
8484
#define TAS2764_TDM_CFG3_RXS_SHIFT 0x4
8585
#define TAS2764_TDM_CFG3_MASK GENMASK(3, 0)
8686

87+
/* TDM Configuration Reg4 */
88+
#define TAS2764_TDM_CFG4 TAS2764_REG(0X0, 0x0d)
89+
#define TAS2764_TDM_CFG4_TX_MASK BIT(0)
90+
#define TAS2764_TDM_CFG4_TX_RISING 0x0
91+
#define TAS2764_TDM_CFG4_TX_FALLING BIT(0)
92+
8793
/* TDM Configuration Reg5 */
8894
#define TAS2764_TDM_CFG5 TAS2764_REG(0X0, 0x0e)
8995
#define TAS2764_TDM_CFG5_VSNS_MASK BIT(6)

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