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bebarinobebarino
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Merge tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Nicolas Ferre: - add one clock for sam9x75 - new meaning for MCR register field in clk-master - use force-write to PLL update register to ensure reliable programming sequence - update Analog Control Register (ACR) management to accommodate differences across SoCs. - ACR management dependency with one ARM PM patch added beforehand * tag 'clk-microchip-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable
2 parents 8f5ae30 + 652b08a commit 1803012

9 files changed

Lines changed: 66 additions & 44 deletions

File tree

‎arch/arm/mach-at91/pm_suspend.S‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -689,6 +689,10 @@ sr_dis_exit:
689689
bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID
690690
str tmp2, [pmc, #AT91_PMC_PLL_UPDT]
691691

692+
/* save acr */
693+
ldr tmp2, [pmc, #AT91_PMC_PLL_ACR]
694+
str tmp2, .saved_acr
695+
692696
/* save div. */
693697
mov tmp1, #0
694698
ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@@ -758,7 +762,7 @@ sr_dis_exit:
758762
str tmp1, [pmc, #AT91_PMC_PLL_UPDT]
759763

760764
/* step 2. */
761-
ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA
765+
ldr tmp1, .saved_acr
762766
str tmp1, [pmc, #AT91_PMC_PLL_ACR]
763767

764768
/* step 3. */
@@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram)
12071211
#endif
12081212
.saved_mckr:
12091213
.word 0
1214+
.saved_acr:
1215+
.word 0
12101216
.saved_pllar:
12111217
.word 0
12121218
.saved_sam9_lpr:

‎drivers/clk/at91/clk-master.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw,
580580
{
581581
struct clk_master *master = to_clk_master(hw);
582582

583+
if (master->div == MASTER_PRES_MAX)
584+
return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);
585+
583586
return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));
584587
}
585588

‎drivers/clk/at91/clk-sam9x60-pll.c‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -93,8 +93,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
9393

9494
spin_lock_irqsave(core->lock, flags);
9595

96-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
97-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
96+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
97+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
9898
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
9999
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
100100
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
@@ -103,11 +103,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
103103
(cmul == frac->mul && cfrac == frac->frac))
104104
goto unlock;
105105

106-
/* Recommended value for PMC_PLL_ACR */
107-
if (core->characteristics->upll)
108-
val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
109-
else
110-
val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
106+
/* Load recommended value for PMC_PLL_ACR */
107+
val = core->characteristics->acr;
111108
regmap_write(regmap, AT91_PMC_PLL_ACR, val);
112109

113110
regmap_write(regmap, AT91_PMC_PLL_CTRL1,
@@ -128,17 +125,17 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
128125
udelay(10);
129126
}
130127

131-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
132-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
133-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
128+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
129+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
130+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
134131

135132
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
136133
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
137134
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
138135

139-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
140-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
141-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
136+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
137+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
138+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
142139

143140
while (!sam9x60_pll_ready(regmap, core->id))
144141
cpu_relax();
@@ -164,18 +161,18 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
164161

165162
spin_lock_irqsave(core->lock, flags);
166163

167-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
168-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
164+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
165+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
169166

170167
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
171168

172169
if (core->characteristics->upll)
173170
regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
174171
AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
175172

176-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
177-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
178-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
173+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
174+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
175+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
179176

180177
spin_unlock_irqrestore(core->lock, flags);
181178
}
@@ -262,8 +259,8 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
262259

263260
spin_lock_irqsave(core->lock, irqflags);
264261

265-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
266-
core->id);
262+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
263+
core->id);
267264
regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
268265
cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
269266
cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
@@ -275,18 +272,18 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
275272
(frac->mul << core->layout->mul_shift) |
276273
(frac->frac << core->layout->frac_shift));
277274

278-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
279-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
280-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
275+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
276+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
277+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
281278

282279
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
283280
AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
284281
AT91_PMC_PLL_CTRL0_ENLOCK |
285282
AT91_PMC_PLL_CTRL0_ENPLL);
286283

287-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
288-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
289-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
284+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
285+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
286+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
290287

291288
while (!sam9x60_pll_ready(regmap, core->id))
292289
cpu_relax();
@@ -338,7 +335,10 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = {
338335
.restore_context = sam9x60_frac_pll_restore_context,
339336
};
340337

341-
/* This function should be called with spinlock acquired. */
338+
/* This function should be called with spinlock acquired.
339+
* Warning: this function must be called only if the same PLL ID was set in
340+
* PLL_UPDT register previously.
341+
*/
342342
static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
343343
bool enable)
344344
{
@@ -350,9 +350,9 @@ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
350350
core->layout->div_mask | ena_msk,
351351
(div << core->layout->div_shift) | ena_val);
352352

353-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
354-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
355-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
353+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
354+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
355+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
356356

357357
while (!sam9x60_pll_ready(regmap, core->id))
358358
cpu_relax();
@@ -366,8 +366,8 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
366366
unsigned int val, cdiv;
367367

368368
spin_lock_irqsave(core->lock, flags);
369-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
370-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
369+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
370+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
371371
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
372372
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
373373

@@ -398,15 +398,15 @@ static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
398398

399399
spin_lock_irqsave(core->lock, flags);
400400

401-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
402-
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
401+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
402+
AT91_PMC_PLL_UPDT_ID_MSK, core->id);
403403

404404
regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
405405
core->layout->endiv_mask, 0);
406406

407-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
408-
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
409-
AT91_PMC_PLL_UPDT_UPDATE | core->id);
407+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,
408+
AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
409+
AT91_PMC_PLL_UPDT_UPDATE | core->id);
410410

411411
spin_unlock_irqrestore(core->lock, flags);
412412
}
@@ -518,8 +518,8 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
518518
div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
519519

520520
spin_lock_irqsave(core->lock, irqflags);
521-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
522-
core->id);
521+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
522+
core->id);
523523
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
524524
cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
525525

@@ -574,8 +574,8 @@ static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
574574
div->div = div->safe_div;
575575

576576
spin_lock_irqsave(core.lock, irqflags);
577-
regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
578-
core.id);
577+
regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
578+
core.id);
579579
regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
580580
cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
581581

‎drivers/clk/at91/pmc.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ struct clk_pll_characteristics {
8080
u16 *icpll;
8181
u8 *out;
8282
u8 upll : 1;
83+
u32 acr;
8384
};
8485

8586
struct clk_programmable_layout {

‎drivers/clk/at91/sam9x60.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
3636
.num_output = ARRAY_SIZE(plla_outputs),
3737
.output = plla_outputs,
3838
.core_output = core_outputs,
39+
.acr = UL(0x00020010),
3940
};
4041

4142
static const struct clk_range upll_outputs[] = {
@@ -48,6 +49,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
4849
.output = upll_outputs,
4950
.core_output = core_outputs,
5051
.upll = true,
52+
.acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
5153
};
5254

5355
static const struct clk_pll_layout pll_frac_layout = {

‎drivers/clk/at91/sam9x7.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -107,6 +107,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
107107
.num_output = ARRAY_SIZE(plla_outputs),
108108
.output = plla_outputs,
109109
.core_output = plla_core_outputs,
110+
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
110111
};
111112

112113
static const struct clk_pll_characteristics upll_characteristics = {
@@ -115,27 +116,31 @@ static const struct clk_pll_characteristics upll_characteristics = {
115116
.output = upll_outputs,
116117
.core_output = upll_core_outputs,
117118
.upll = true,
119+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
118120
};
119121

120122
static const struct clk_pll_characteristics lvdspll_characteristics = {
121123
.input = { .min = 20000000, .max = 50000000 },
122124
.num_output = ARRAY_SIZE(lvdspll_outputs),
123125
.output = lvdspll_outputs,
124126
.core_output = lvdspll_core_outputs,
127+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
125128
};
126129

127130
static const struct clk_pll_characteristics audiopll_characteristics = {
128131
.input = { .min = 20000000, .max = 50000000 },
129132
.num_output = ARRAY_SIZE(audiopll_outputs),
130133
.output = audiopll_outputs,
131134
.core_output = audiopll_core_outputs,
135+
.acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
132136
};
133137

134138
static const struct clk_pll_characteristics plladiv2_characteristics = {
135139
.input = { .min = 20000000, .max = 50000000 },
136140
.num_output = ARRAY_SIZE(plladiv2_outputs),
137141
.output = plladiv2_outputs,
138142
.core_output = plladiv2_core_outputs,
143+
.acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
139144
};
140145

141146
/* Layout for fractional PLL ID PLLA. */
@@ -403,6 +408,7 @@ static const struct {
403408
{ .n = "pioD_clk", .id = 44, },
404409
{ .n = "tcb1_clk", .id = 45, },
405410
{ .n = "dbgu_clk", .id = 47, },
411+
{ .n = "pmecc_clk", .id = 48, },
406412
/*
407413
* mpddr_clk feeds DDR controller and is enabled by bootloader thus we
408414
* need to keep it enabled in case there is no Linux consumer for it.

‎drivers/clk/at91/sama7d65.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
138138
.num_output = ARRAY_SIZE(cpu_pll_outputs),
139139
.output = cpu_pll_outputs,
140140
.core_output = core_outputs,
141+
.acr = UL(0x00070010),
141142
};
142143

143144
/* PLL characteristics. */
@@ -146,20 +147,23 @@ static const struct clk_pll_characteristics pll_characteristics = {
146147
.num_output = ARRAY_SIZE(pll_outputs),
147148
.output = pll_outputs,
148149
.core_output = core_outputs,
150+
.acr = UL(0x00070010),
149151
};
150152

151153
static const struct clk_pll_characteristics lvdspll_characteristics = {
152154
.input = { .min = 12000000, .max = 50000000 },
153155
.num_output = ARRAY_SIZE(lvdspll_outputs),
154156
.output = lvdspll_outputs,
155157
.core_output = lvdspll_core_outputs,
158+
.acr = UL(0x00070010),
156159
};
157160

158161
static const struct clk_pll_characteristics upll_characteristics = {
159162
.input = { .min = 20000000, .max = 50000000 },
160163
.num_output = ARRAY_SIZE(upll_outputs),
161164
.output = upll_outputs,
162165
.core_output = upll_core_outputs,
166+
.acr = UL(0x12020010),
163167
.upll = true,
164168
};
165169

‎drivers/clk/at91/sama7g5.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
113113
.num_output = ARRAY_SIZE(cpu_pll_outputs),
114114
.output = cpu_pll_outputs,
115115
.core_output = core_outputs,
116+
.acr = UL(0x00070010),
116117
};
117118

118119
/* PLL characteristics. */
@@ -121,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
121122
.num_output = ARRAY_SIZE(pll_outputs),
122123
.output = pll_outputs,
123124
.core_output = core_outputs,
125+
.acr = UL(0x00070010),
124126
};
125127

126128
/*

‎include/linux/clk/at91_pmc.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -47,8 +47,6 @@
4747
#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */
4848

4949
#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */
50-
#define AT91_PMC_PLL_ACR_DEFAULT_UPLL UL(0x12020010) /* Default PLL ACR value for UPLL */
51-
#define AT91_PMC_PLL_ACR_DEFAULT_PLLA UL(0x00020010) /* Default PLL ACR value for PLLA */
5250
#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */
5351
#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */
5452

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