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akhilpo-qcomRob Clark
akhilpo-qcom
authored and
Rob Clark
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drm/msm/a6xx: Sync latest register definitions
Sync the latest register definitions from Mesa which includes the updates for A8x family. Co-developed-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689009/ Message-ID: <20251118-kaana-gpu-support-v4-9-86eeb8e93fb6@oss.qualcomm.com>
1 parent 0d9f5ee commit 1ef05ef

12 files changed

Lines changed: 2339 additions & 691 deletions

‎drivers/gpu/drm/msm/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,7 @@ ADRENO_HEADERS = \
201201
generated/a6xx_perfcntrs.xml.h \
202202
generated/a7xx_enums.xml.h \
203203
generated/a7xx_perfcntrs.xml.h \
204+
generated/a8xx_enums.xml.h \
204205
generated/a6xx_gmu.xml.h \
205206
generated/adreno_common.xml.h \
206207
generated/adreno_pm4.xml.h \

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -238,7 +238,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
238238
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);
239239

240240
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
241-
OUT_RING(ring, LRZ_FLUSH);
241+
OUT_RING(ring, LRZ_FLUSH_INVALIDATE);
242242

243243
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
244244
OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);
@@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
381381
rbmemptr_stats(ring, index, alwayson_end));
382382

383383
/* Write the fence to the scratch register */
384-
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
384+
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
385385
OUT_RING(ring, submit->seqno);
386386

387387
/*
@@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
522522
rbmemptr_stats(ring, index, alwayson_end));
523523

524524
/* Write the fence to the scratch register */
525-
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
525+
OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1);
526526
OUT_RING(ring, submit->seqno);
527527

528528
OUT_PKT7(ring, CP_THREAD_CONTROL, 1);
@@ -1305,7 +1305,7 @@ static int hw_init(struct msm_gpu *gpu)
13051305
}
13061306

13071307
if (adreno_is_a660_family(adreno_gpu))
1308-
gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1308+
gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
13091309

13101310
/* Setting the mem pool size */
13111311
if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
@@ -1754,10 +1754,10 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da
17541754
const char *block = "unknown";
17551755

17561756
u32 scratch[] = {
1757-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1758-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1759-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1760-
gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)),
1757+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)),
1758+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)),
1759+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)),
1760+
gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)),
17611761
};
17621762

17631763
if (info)

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,8 @@ static const struct a6xx_cluster {
7171
u32 sel_val;
7272
} a6xx_clusters[] = {
7373
CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0),
74-
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
75-
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
74+
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0),
75+
CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9),
7676
CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0),
7777
CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0),
7878
CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0),
@@ -303,8 +303,8 @@ static const u32 a660_registers[] = {
303303
static const struct a6xx_registers a6xx_reglist[] = {
304304
REGS(a6xx_registers, 0, 0),
305305
REGS(a660_registers, 0, 0),
306-
REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307-
REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
306+
REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0),
307+
REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9),
308308
};
309309

310310
static const u32 a6xx_ahb_registers[] = {

‎drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
691691
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));
692692

693693
static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = {
694-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
695-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
694+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
695+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
696696
.val = 0x0,
697697
};
698698

699699
static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
700-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
701-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
700+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
701+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
702702
.val = 0x9,
703703
};
704704

‎drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
478478
static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
479479

480480
static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = {
481-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
482-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
481+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
482+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
483483
.val = 0x0,
484484
};
485485

486486
static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
487-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
488-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
487+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
488+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
489489
.val = 0x9,
490490
};
491491

‎drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1105,14 +1105,14 @@ static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = {
11051105
static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8));
11061106

11071107
static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = {
1108-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
1109-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
1108+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
1109+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
11101110
.val = 0,
11111111
};
11121112

11131113
static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = {
1114-
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
1115-
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
1114+
.host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST,
1115+
.cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD,
11161116
.val = 0x9,
11171117
};
11181118

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