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Sumit Guptathierryreding
Sumit Gupta
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thierryreding
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memory: tegra: Add Tegra264 MC and EMC support
Add support to enable Memory Controller (MC) and External Memory Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are mostly the same as Tegra234 but differ in number of channels and interrupt numbers. The patch also adds the bandwidth manager definitions required for Tegra264 and uses them to populate the memory client table. All of these are needed to properly enable memory interconnect (ICC) support. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
1 parent 1f7bc0e commit 2401dc4

7 files changed

Lines changed: 395 additions & 6 deletions

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‎drivers/memory/tegra/Makefile‎

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@@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
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tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186.o tegra264.o
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obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
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@@ -21,5 +22,6 @@ obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
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obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o
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obj-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186-emc.o
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tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o

‎drivers/memory/tegra/mc.c‎

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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
3-
* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
@@ -48,6 +48,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
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#endif
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#ifdef CONFIG_ARCH_TEGRA_234_SOC
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{ .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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{ .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc },
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#endif
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{ /* sentinel */ }
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};

‎drivers/memory/tegra/mc.h‎

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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef MEMORY_TEGRA_MC_H
@@ -182,6 +182,10 @@ extern const struct tegra_mc_soc tegra194_mc_soc;
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extern const struct tegra_mc_soc tegra234_mc_soc;
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#endif
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#ifdef CONFIG_ARCH_TEGRA_264_SOC
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extern const struct tegra_mc_soc tegra264_mc_soc;
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#endif
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#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
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defined(CONFIG_ARCH_TEGRA_114_SOC) || \
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defined(CONFIG_ARCH_TEGRA_124_SOC) || \
@@ -193,7 +197,8 @@ extern const struct tegra_mc_ops tegra30_mc_ops;
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#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
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defined(CONFIG_ARCH_TEGRA_194_SOC) || \
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defined(CONFIG_ARCH_TEGRA_234_SOC)
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defined(CONFIG_ARCH_TEGRA_234_SOC) || \
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defined(CONFIG_ARCH_TEGRA_264_SOC)
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extern const struct tegra_mc_ops tegra186_mc_ops;
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#endif
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‎drivers/memory/tegra/tegra186-emc.c‎

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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
3-
* Copyright (C) 2019 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2019-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/clk.h>
@@ -393,6 +393,9 @@ static const struct of_device_id tegra186_emc_of_match[] = {
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#endif
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#if defined(CONFIG_ARCH_TEGRA_234_SOC)
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{ .compatible = "nvidia,tegra234-emc" },
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#endif
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#if defined(CONFIG_ARCH_TEGRA_264_SOC)
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{ .compatible = "nvidia,tegra264-emc" },
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#endif
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{ /* sentinel */ }
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};

‎drivers/memory/tegra/tegra186.c‎

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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
3-
* Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
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* Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
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*/
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#include <linux/io.h>
@@ -26,11 +26,24 @@
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static int tegra186_mc_probe(struct tegra_mc *mc)
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{
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struct platform_device *pdev = to_platform_device(mc->dev);
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struct resource *res;
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unsigned int i;
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char name[8];
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int err;
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mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
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/*
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* From Tegra264, the SID region is not present in MC node and BROADCAST is first.
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* The common function 'tegra_mc_probe()' already maps first region entry from DT.
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* Check if the SID region is present in DT then map BROADCAST. Otherwise, consider
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* the first entry mapped in mc probe as the BROADCAST region. This is done to avoid
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* mapping the region twice when SID is not present and keep backward compatibility.
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*/
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
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if (res)
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mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
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else
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mc->bcast_ch_regs = mc->regs;
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if (IS_ERR(mc->bcast_ch_regs)) {
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if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
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dev_warn(&pdev->dev,

‎drivers/memory/tegra/tegra264-bwmgr.h‎

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@@ -0,0 +1,50 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2025 NVIDIA CORPORATION. All rights reserved. */
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#ifndef MEMORY_TEGRA_TEGRA264_BWMGR_H
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#define MEMORY_TEGRA_TEGRA264_BWMGR_H
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#define TEGRA264_BWMGR_ICC_PRIMARY 1
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#define TEGRA264_BWMGR_DEBUG 2
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#define TEGRA264_BWMGR_CPU_CLUSTER0 3
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#define TEGRA264_BWMGR_CPU_CLUSTER1 4
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#define TEGRA264_BWMGR_CPU_CLUSTER2 5
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#define TEGRA264_BWMGR_CPU_CLUSTER3 6
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#define TEGRA264_BWMGR_CPU_CLUSTER4 7
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#define TEGRA264_BWMGR_CPU_CLUSTER5 8
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#define TEGRA264_BWMGR_CPU_CLUSTER6 9
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#define TEGRA264_BWMGR_CACTMON 10
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#define TEGRA264_BWMGR_DISPLAY 11
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#define TEGRA264_BWMGR_VI 12
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#define TEGRA264_BWMGR_APE 13
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#define TEGRA264_BWMGR_VIFAL 14
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#define TEGRA264_BWMGR_GPU 15
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#define TEGRA264_BWMGR_EQOS 16
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#define TEGRA264_BWMGR_PCIE_0 17
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#define TEGRA264_BWMGR_PCIE_1 18
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#define TEGRA264_BWMGR_PCIE_2 19
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#define TEGRA264_BWMGR_PCIE_3 20
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#define TEGRA264_BWMGR_PCIE_4 21
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#define TEGRA264_BWMGR_PCIE_5 22
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#define TEGRA264_BWMGR_SDMMC_1 23
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#define TEGRA264_BWMGR_SDMMC_2 24
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#define TEGRA264_BWMGR_NVDEC 25
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#define TEGRA264_BWMGR_NVENC 26
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#define TEGRA264_BWMGR_NVJPG_0 27
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#define TEGRA264_BWMGR_NVJPG_1 28
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#define TEGRA264_BWMGR_OFAA 29
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#define TEGRA264_BWMGR_XUSB_HOST 30
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#define TEGRA264_BWMGR_XUSB_DEV 31
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#define TEGRA264_BWMGR_TSEC 32
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#define TEGRA264_BWMGR_VIC 33
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#define TEGRA264_BWMGR_APEDMA 34
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#define TEGRA264_BWMGR_SE 35
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#define TEGRA264_BWMGR_ISP 36
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#define TEGRA264_BWMGR_HDA 37
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#define TEGRA264_BWMGR_VI2FAL 38
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#define TEGRA264_BWMGR_VI2 39
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#define TEGRA264_BWMGR_RCE 40
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#define TEGRA264_BWMGR_PVA 41
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#define TEGRA264_BWMGR_NVPMODEL 42
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#endif

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