drm/amd/ras: Update function and remove redundant code

Update function and remove redundant code:
1. Update function to prepare for internal use.
2. Remove unused function code previously prepared
   for ioctl.

V2:
  Update commit message content.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Author: YiPeng Chai

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.c

@@ -36,67 +36,6 @@
 #define AMDGPU_RAS_TYPE_AMDGPU   0x2
 #define AMDGPU_RAS_TYPE_VF       0x3
 
-static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core,
-			struct ras_cmd_ctx *cmd)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
-	struct ras_query_interface_info_rsp *output_data =
-		(struct ras_query_interface_info_rsp *)cmd->output_buff_raw;
-	int ret;
-
-	if (cmd->input_size != sizeof(struct ras_query_interface_info_req))
-		return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
-
-	ret = ras_cmd_query_interface_info(ras_core, output_data);
-	if (!ret) {
-		output_data->plat_major_ver = 0;
-		output_data->plat_minor_ver = 0;
-
-		output_data->interface_type = amdgpu_sriov_vf(adev) ?
-			RAS_CMD_INTERFACE_TYPE_VF : RAS_CMD_INTERFACE_TYPE_AMDGPU;
-
-		cmd->output_size = sizeof(struct ras_query_interface_info_rsp);
-	}
-
-	return ret;
-}
-
-static struct ras_core_context *ras_cmd_get_ras_core(uint64_t dev_handle)
-{
-	struct ras_core_context *ras_core;
-
-	if (!dev_handle || (dev_handle == RAS_CMD_DEV_HANDLE_MAGIC))
-		return NULL;
-
-	ras_core = (struct ras_core_context *)(uintptr_t)(dev_handle ^ RAS_CMD_DEV_HANDLE_MAGIC);
-
-	if (ras_cmd_get_dev_handle(ras_core) == dev_handle)
-		return ras_core;
-
-	return NULL;
-}
-
-static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core,
-			struct ras_cmd_ctx *cmd)
-{
-	struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
-	struct ras_cmd_devices_info_rsp *output_data =
-			(struct ras_cmd_devices_info_rsp *)cmd->output_buff_raw;
-	struct ras_cmd_dev_info *dev_info;
-
-	dev_info = &output_data->devs[0];
-	dev_info->dev_handle = ras_cmd_get_dev_handle(ras_core);
-	dev_info->oam_id = adev->smuio.funcs->get_socket_id(adev);
-	dev_info->ecc_enabled = 1;
-	dev_info->ecc_supported = 1;
-
-	output_data->dev_num = 1;
-	output_data->version = 0;
-	cmd->output_size = sizeof(struct ras_cmd_devices_info_rsp);
-
-	return 0;
-}
-
 static int amdgpu_ras_trigger_error_prepare(struct ras_core_context *ras_core,
 			struct ras_cmd_inject_error_req *block_info)
 {
@@ -311,51 +250,34 @@ int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx
 	return res;
 }
 
-int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
-			uint8_t *cmd_buf, uint32_t buf_size)
+int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd)
 {
-	struct ras_cmd_ctx *cmd = (struct ras_cmd_ctx *)cmd_buf;
-	struct ras_core_context *cmd_core = NULL;
-	struct ras_cmd_dev_handle *cmd_handle = NULL;
+	struct ras_core_context *cmd_core = ras_core;
 	int timeout = 60;
 	int res;
 
 	cmd->cmd_res = RAS_CMD__ERROR_INVALID_CMD;
 	cmd->output_size = 0;
 
-	if (!ras_core_is_enabled(ras_core))
+	if (!ras_core_is_enabled(cmd_core))
 		return RAS_CMD__ERROR_ACCESS_DENIED;
 
-	if (cmd->cmd_id == RAS_CMD__QUERY_INTERFACE_INFO) {
-		cmd->cmd_res = amdgpu_ras_query_interface_info(ras_core, cmd);
-	} else if (cmd->cmd_id == RAS_CMD__GET_DEVICES_INFO) {
-		cmd->cmd_res = amdgpu_ras_get_devices_info(ras_core, cmd);
-	} else {
-		cmd_handle = (struct ras_cmd_dev_handle *)cmd->input_buff_raw;
-		cmd_core = ras_cmd_get_ras_core(cmd_handle->dev_handle);
-		if (!cmd_core)
-			return RAS_CMD__ERROR_INVALID_INPUT_DATA;
-
-		while (ras_core_gpu_in_reset(cmd_core)) {
-			msleep(1000);
-			if (!timeout--)
-				return RAS_CMD__ERROR_TIMEOUT;
-		}
-
-
-		if (!ras_core_is_enabled(cmd_core))
-			return RAS_CMD__ERROR_ACCESS_DENIED;
+	while (ras_core_gpu_in_reset(cmd_core)) {
+		msleep(1000);
+		if (!timeout--)
+			return RAS_CMD__ERROR_TIMEOUT;
+	}
 
-		res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL);
-		if (res == RAS_CMD__ERROR_UKNOWN_CMD)
-			res = rascore_handle_cmd(cmd_core, cmd, NULL);
+	res = amdgpu_ras_handle_cmd(cmd_core, cmd, NULL);
+	if (res == RAS_CMD__ERROR_UKNOWN_CMD)
+		res = rascore_handle_cmd(cmd_core, cmd, NULL);
 
-		cmd->cmd_res = res;
-	}
+	cmd->cmd_res = res;
 
-	if ((cmd->cmd_res == RAS_CMD__SUCCESS) &&
-	    ((cmd->output_size + sizeof(*cmd)) > buf_size)) {
-		RAS_INFO("Insufficient command buffer size 0x%x!\n", buf_size);
+	if (cmd->output_size > cmd->output_buf_size) {
+		RAS_DEV_ERR(cmd_core->dev,
+			"Output size 0x%x exceeds output buffer size 0x%x!\n",
+			cmd->output_size, cmd->output_buf_size);
 		return RAS_CMD__SUCCESS_EXEED_BUFFER;
 	}
 

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_cmd.h

@@ -49,7 +49,6 @@ struct ras_cmd_translate_memory_fd_rsp {
 
 int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core,
 		struct ras_cmd_ctx *cmd, void *data);
-int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
-			uint8_t *cmd_buf, uint32_t buf_size);
+int amdgpu_ras_submit_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd);
 
 #endif

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

@@ -578,3 +578,34 @@ bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev)
 
 	return ras_core_gpu_is_rma(ras_mgr->ras_core);
 }
+
+int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev,
+			uint32_t cmd_id, void *input, uint32_t input_size,
+			void *output, uint32_t out_size)
+{
+	struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
+	struct ras_cmd_ctx *cmd_ctx;
+	uint32_t ctx_buf_size = PAGE_SIZE;
+	int ret;
+
+	if (!amdgpu_ras_mgr_is_ready(adev))
+		return -EPERM;
+
+	cmd_ctx = kzalloc(ctx_buf_size, GFP_KERNEL);
+	if (!cmd_ctx)
+		return -ENOMEM;
+
+	cmd_ctx->cmd_id = cmd_id;
+
+	memcpy(cmd_ctx->input_buff_raw, input, input_size);
+	cmd_ctx->input_size = input_size;
+	cmd_ctx->output_buf_size = ctx_buf_size - sizeof(*cmd_ctx);
+
+	ret = amdgpu_ras_submit_cmd(ras_mgr->ras_core, cmd_ctx);
+	if (!ret && !cmd_ctx->cmd_res && output && (out_size == cmd_ctx->output_size))
+		memcpy(output, cmd_ctx->output_buff_raw, cmd_ctx->output_size);
+
+	kfree(cmd_ctx);
+
+	return ret;
+}

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

@@ -72,4 +72,7 @@ int amdgpu_ras_mgr_get_curr_nps_mode(struct amdgpu_device *adev, uint32_t *nps_m
 bool amdgpu_ras_mgr_check_retired_addr(struct amdgpu_device *adev,
 			uint64_t addr);
 bool amdgpu_ras_mgr_is_rma(struct amdgpu_device *adev);
+int amdgpu_ras_mgr_handle_ras_cmd(struct amdgpu_device *adev,
+		uint32_t cmd_id, void *input, uint32_t input_size,
+		void *output, uint32_t out_size);
 #endif

drivers/gpu/drm/amd/ras/rascore/ras_cmd.h

@@ -153,7 +153,8 @@ struct ras_cmd_ctx {
 	uint32_t cmd_res;
 	uint32_t input_size;
 	uint32_t output_size;
-	uint32_t reserved[6];
+	uint32_t output_buf_size;
+	uint32_t reserved[5];
 	uint8_t  input_buff_raw[RAS_CMD_MAX_IN_SIZE];
 	uint8_t  output_buff_raw[];
 };

drivers/gpu/drm/amd/ras/rascore/ras_core.c

@@ -62,7 +62,8 @@ int ras_core_convert_timestamp_to_time(struct ras_core_context *ras_core,
 			uint64_t timestamp, struct ras_time *tm)
 {
 	int days_in_month[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
-	uint64_t year = 0, month = 0, day = 0, hour = 0, minute = 0, second = 0;
+	uint64_t month = 0, day = 0, hour = 0, minute = 0, second = 0;
+	uint32_t year = 0;
 	int seconds_per_day = 24 * 60 * 60;
 	int seconds_per_hour = 60 * 60;
 	int seconds_per_minute = 60;

drivers/gpu/drm/amd/ras/rascore/ras_eeprom.c

@@ -199,17 +199,6 @@ static int __ras_eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr,
 	return -EINVAL;
 }
 
-
-/**
- * __eeprom_xfer -- Read/write from/to an I2C EEPROM device
- * @i2c_adap: pointer to the I2C adapter to use
- * @eeprom_addr: EEPROM address from which to read/write
- * @eeprom_buf: pointer to data buffer to read into/write from
- * @buf_size: the size of @eeprom_buf
- * @read: True if reading from the EEPROM, false if writing
- *
- * Returns the number of bytes read/written; -errno on error.
- */
 static int __eeprom_xfer(struct ras_core_context *ras_core, u32 eeprom_addr,
 			      u8 *eeprom_buf, u32 buf_size, bool read)
 {
@@ -454,13 +443,6 @@ static void ras_set_eeprom_table_version(struct ras_eeprom_control *control)
 	hdr->version = RAS_TABLE_VER_V3;
 }
 
-/**
- * ras_eeprom_reset_table -- Reset the RAS EEPROM table
- * @control: pointer to control structure
- *
- * Reset the contents of the header of the RAS EEPROM table.
- * Return 0 on success, -errno on error.
- */
 int ras_eeprom_reset_table(struct ras_core_context *ras_core)
 {
 	struct ras_eeprom_control *control = &ras_core->ras_eeprom;
@@ -928,17 +910,6 @@ static int __ras_eeprom_read(struct ras_eeprom_control *control,
 	return res;
 }
 
-/**
- * ras_eeprom_read -- read EEPROM
- * @control: pointer to control structure
- * @record: array of records to read into
- * @num: number of records in @record
- *
- * Reads num records from the RAS table in EEPROM and
- * writes the data into @record array.
- *
- * Returns 0 on success, -errno on error.
- */
 int ras_eeprom_read(struct ras_core_context *ras_core,
 			 struct eeprom_umc_record *record, const u32 num)
 {