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phy: qcom: sgmii-eth: move PCS registers to separate header
Follow the example of the rest of the QMP PHY drivers and move SGMII PCS registers to a separate header file. Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-8-a463d0b57836@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
1 parent df71879 commit 25ee21f

2 files changed

Lines changed: 47 additions & 37 deletions

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‎drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
/* SPDX-License-Identifier: GPL-2.0 */
2+
/*
3+
* Copyright (c) 2023, Linaro Limited
4+
*/
5+
6+
#ifndef QCOM_PHY_QMP_PCS_SGMII_H_
7+
#define QCOM_PHY_QMP_PCS_SGMII_H_
8+
9+
#define QPHY_PCS_PHY_START 0x000
10+
#define QPHY_PCS_POWER_DOWN_CONTROL 0x004
11+
#define QPHY_PCS_SW_RESET 0x008
12+
#define QPHY_PCS_LINE_RESET_TIME 0x00c
13+
#define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020
14+
#define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028
15+
#define QPHY_PCS_PCS_READY_STATUS 0x094
16+
#define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8
17+
#define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc
18+
#define QPHY_PCS_SGMII_MISC_CTRL8 0x118
19+
20+
#endif

‎drivers/phy/qualcomm/phy-qcom-sgmii-eth.c‎

Lines changed: 27 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <linux/platform_device.h>
1212
#include <linux/regmap.h>
1313

14+
#include "phy-qcom-qmp-pcs-sgmii.h"
1415
#include "phy-qcom-qmp-qserdes-com-v5.h"
1516
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
1617

@@ -19,17 +20,6 @@
1920
#define QSERDES_TX 0x400
2021
#define QSERDES_PCS 0xc00
2122

22-
#define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0)
23-
#define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4)
24-
#define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8)
25-
#define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc)
26-
#define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20)
27-
#define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28)
28-
#define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8)
29-
#define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc)
30-
#define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118)
31-
#define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94)
32-
3323
#define QSERDES_COM_C_READY BIT(0)
3424
#define QSERDES_PCS_READY BIT(0)
3525
#define QSERDES_PCS_SGMIIPHY_READY BIT(7)
@@ -43,8 +33,8 @@ struct qcom_dwmac_sgmii_phy_data {
4333

4434
static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap)
4535
{
46-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
47-
regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
36+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
37+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
4838

4939
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
5040
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
@@ -118,21 +108,21 @@ static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap)
118108
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
119109
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
120110

121-
regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
122-
regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
123-
regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
124-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
125-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
126-
regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C);
127-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
111+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
112+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
113+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
114+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
115+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
116+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C);
117+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
128118

129-
regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
119+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
130120
}
131121

132122
static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap)
133123
{
134-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01);
135-
regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01);
124+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
125+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01);
136126

137127
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F);
138128
regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06);
@@ -206,15 +196,15 @@ static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap)
206196
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7);
207197
regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C);
208198

209-
regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C);
210-
regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
211-
regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
212-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83);
213-
regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
214-
regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C);
215-
regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00);
199+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C);
200+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F);
201+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03);
202+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83);
203+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
204+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C);
205+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
216206

217-
regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01);
207+
regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
218208
}
219209

220210
static inline int
@@ -251,14 +241,14 @@ static int qcom_dwmac_sgmii_phy_calibrate(struct phy *phy)
251241
}
252242

253243
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
254-
QSERDES_PCS_PCS_READY_STATUS,
244+
QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
255245
QSERDES_PCS_READY)) {
256246
dev_err(dev, "PCS_READY timed-out");
257247
return -ETIMEDOUT;
258248
}
259249

260250
if (qcom_dwmac_sgmii_phy_poll_status(data->regmap,
261-
QSERDES_PCS_PCS_READY_STATUS,
251+
QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS,
262252
QSERDES_PCS_SGMIIPHY_READY)) {
263253
dev_err(dev, "SGMIIPHY_READY timed-out");
264254
return -ETIMEDOUT;
@@ -285,11 +275,11 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy)
285275
{
286276
struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
287277

288-
regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08);
289-
regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01);
278+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08);
279+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01);
290280
udelay(100);
291-
regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00);
292-
regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01);
281+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00);
282+
regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01);
293283

294284
clk_disable_unprepare(data->refclk);
295285

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