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cxl/events: Promote CXL event structures to a core header
UEFI code can process CXL events through CPER records. Those records use almost the same format as the CXL events. Lift the CXL event structures to a core header to be shared in later patches. [jic123: drop "CXL rev 3.0" mention] Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/20231220-cxl-cper-v5-2-1bb8a4ca2c7a@intel.com [djbw: add F: entry to maintainers for include/linux/cxl-event.h] Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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‎MAINTAINERS‎

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@@ -5245,6 +5245,7 @@ M: Dan Williams <dan.j.williams@intel.com>
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L: linux-cxl@vger.kernel.org
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S: Maintained
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F: drivers/cxl/
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F: include/linux/cxl-event.h
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F: include/uapi/linux/cxl_mem.h
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F: tools/testing/cxl/
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‎drivers/cxl/cxlmem.h‎

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#include <linux/cdev.h>
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#include <linux/uuid.h>
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#include <linux/rcuwait.h>
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#include <linux/cxl-event.h>
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#include "cxl.h"
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/* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
@@ -579,27 +580,6 @@ struct cxl_mbox_identify {
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u8 qos_telemetry_caps;
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} __packed;
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/*
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* Common Event Record Format
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_hdr {
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uuid_t id;
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u8 length;
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u8 flags[3];
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__le16 handle;
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__le16 related_handle;
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__le64 timestamp;
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u8 maint_op_class;
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u8 reserved[15];
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} __packed;
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#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
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struct cxl_event_record_raw {
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struct cxl_event_record_hdr hdr;
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u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
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} __packed;
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/*
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* Get Event Records output payload
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* CXL rev 3.0 section 8.2.9.2.2; Table 8-50
@@ -641,74 +621,6 @@ struct cxl_mbox_clear_event_payload {
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} __packed;
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#define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
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/*
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* General Media Event Record
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* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
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*/
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#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
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struct cxl_event_gen_media {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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u8 device[3];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 reserved[46];
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} __packed;
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/*
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* DRAM Event Record - DER
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* CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
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*/
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#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
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struct cxl_event_dram {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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u8 nibble_mask[3];
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u8 bank_group;
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u8 bank;
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u8 row[3];
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u8 column[2];
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u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
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u8 reserved[0x17];
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} __packed;
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/*
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* Get Health Info Record
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* CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
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*/
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struct cxl_get_health_info {
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u8 health_status;
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u8 media_status;
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u8 add_status;
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u8 life_used;
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u8 device_temp[2];
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u8 dirty_shutdown_cnt[4];
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u8 cor_vol_err_cnt[4];
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u8 cor_per_err_cnt[4];
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} __packed;
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/*
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* Memory Module Event Record
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* CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
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*/
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struct cxl_event_mem_module {
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struct cxl_event_record_hdr hdr;
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u8 event_type;
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struct cxl_get_health_info info;
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u8 reserved[0x3d];
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} __packed;
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struct cxl_mbox_get_partition_info {
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__le64 active_volatile_cap;
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__le64 active_persistent_cap;

‎include/linux/cxl-event.h‎

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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2023 Intel Corporation. */
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#ifndef _LINUX_CXL_EVENT_H
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#define _LINUX_CXL_EVENT_H
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/*
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* Common Event Record Format
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* CXL rev 3.0 section 8.2.9.2.1; Table 8-42
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*/
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struct cxl_event_record_hdr {
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uuid_t id;
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u8 length;
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u8 flags[3];
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__le16 handle;
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__le16 related_handle;
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__le64 timestamp;
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u8 maint_op_class;
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u8 reserved[15];
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} __packed;
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#define CXL_EVENT_RECORD_DATA_LENGTH 0x50
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struct cxl_event_record_raw {
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struct cxl_event_record_hdr hdr;
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u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
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} __packed;
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/*
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* General Media Event Record
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* CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
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*/
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#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
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struct cxl_event_gen_media {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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u8 device[3];
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u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
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u8 reserved[46];
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} __packed;
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/*
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* DRAM Event Record - DER
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* CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
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*/
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#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
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struct cxl_event_dram {
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struct cxl_event_record_hdr hdr;
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__le64 phys_addr;
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u8 descriptor;
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u8 type;
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u8 transaction_type;
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u8 validity_flags[2];
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u8 channel;
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u8 rank;
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u8 nibble_mask[3];
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u8 bank_group;
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u8 bank;
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u8 row[3];
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u8 column[2];
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u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
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u8 reserved[0x17];
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} __packed;
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/*
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* Get Health Info Record
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* CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
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*/
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struct cxl_get_health_info {
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u8 health_status;
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u8 media_status;
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u8 add_status;
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u8 life_used;
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u8 device_temp[2];
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u8 dirty_shutdown_cnt[4];
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u8 cor_vol_err_cnt[4];
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u8 cor_per_err_cnt[4];
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} __packed;
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/*
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* Memory Module Event Record
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* CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
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*/
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struct cxl_event_mem_module {
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struct cxl_event_record_hdr hdr;
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u8 event_type;
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struct cxl_get_health_info info;
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u8 reserved[0x3d];
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} __packed;
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#endif /* _LINUX_CXL_EVENT_H */

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