drm/xe: Move LRC_ENGINE_ID_PPHWSP_OFFSET outside of parallel offset

mbrost05 · mbrost05 · commit 2e273e4f8555 · 2025-06-17T08:25:58.000-07:00
The parallel scratch layout spans 2k and LRC_ENGINE_ID_PPHWSP_OFFSET lands within than space. This happens to be ok as the offset lands in reserved part of guc_sched_wq_desc, but for future safety move LRC_ENGINE_ID_PPHWSP_OFFSET to the unused offset of 1024 below parallel scratch layout. Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://lore.kernel.org/r/20250612172850.4170428-1-matthew.brost@intel.com
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
@@ -655,8 +655,8 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)
 #define LRC_SEQNO_PPHWSP_OFFSET 512
 #define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)
 #define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)
+#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024
 #define LRC_PARALLEL_PPHWSP_OFFSET 2048
-#define LRC_ENGINE_ID_PPHWSP_OFFSET 2096
 
 u32 xe_lrc_regs_offset(struct xe_lrc *lrc)
 {

Original file line number	Diff line number	Diff line change
`@@ -655,8 +655,8 @@ u32 xe_lrc_pphwsp_offset(struct xe_lrc *lrc)`
`655`	`655`	`#define LRC_SEQNO_PPHWSP_OFFSET 512`
`656`	`656`	`#define LRC_START_SEQNO_PPHWSP_OFFSET (LRC_SEQNO_PPHWSP_OFFSET + 8)`
`657`	`657`	`#define LRC_CTX_JOB_TIMESTAMP_OFFSET (LRC_START_SEQNO_PPHWSP_OFFSET + 8)`
	`658`	`+#define LRC_ENGINE_ID_PPHWSP_OFFSET 1024`
`658`	`659`	`#define LRC_PARALLEL_PPHWSP_OFFSET 2048`
`659`		`-#define LRC_ENGINE_ID_PPHWSP_OFFSET 2096`
`660`	`660`
`661`	`661`	`u32 xe_lrc_regs_offset(struct xe_lrc *lrc)`
`662`	`662`	`{`