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clk: mediatek: Add MT8196 vdecsys clock support
Add support for the MT8196 vdecsys clock controller, which provides clock gate control for the video decoder. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/Kconfig‎

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@@ -1059,6 +1059,13 @@ config COMMON_CLK_MT8196_UFSSYS
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help
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This driver supports MediaTek MT8196 ufssys clocks.
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config COMMON_CLK_MT8196_VDECSYS
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tristate "Clock driver for MediaTek MT8196 vdecsys"
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depends on COMMON_CLK_MT8196
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default m
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help
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This driver supports MediaTek MT8196 vdecsys clocks.
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config COMMON_CLK_MT8365
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tristate "Clock driver for MediaTek MT8365"
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depends on ARCH_MEDIATEK || COMPILE_TEST

‎drivers/clk/mediatek/Makefile‎

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@@ -161,6 +161,7 @@ obj-$(CONFIG_COMMON_CLK_MT8196_MMSYS) += clk-mt8196-disp0.o clk-mt8196-disp1.o c
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clk-mt8196-ovl0.o clk-mt8196-ovl1.o
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obj-$(CONFIG_COMMON_CLK_MT8196_PEXTPSYS) += clk-mt8196-pextp.o
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obj-$(CONFIG_COMMON_CLK_MT8196_UFSSYS) += clk-mt8196-ufs_ao.o
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obj-$(CONFIG_COMMON_CLK_MT8196_VDECSYS) += clk-mt8196-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
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obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
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obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o

‎drivers/clk/mediatek/clk-mt8196-vdec.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Guangjie Song <guangjie.song@mediatek.com>
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* Copyright (c) 2025 Collabora Ltd.
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* Laura Nao <laura.nao@collabora.com>
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*/
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#include <dt-bindings/clock/mediatek,mt8196-clock.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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static const struct mtk_gate_regs vde20_cg_regs = {
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.set_ofs = 0x0,
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.clr_ofs = 0x4,
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.sta_ofs = 0x0,
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};
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static const struct mtk_gate_regs vde20_hwv_regs = {
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.set_ofs = 0x0088,
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.clr_ofs = 0x008c,
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.sta_ofs = 0x2c44,
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};
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static const struct mtk_gate_regs vde21_cg_regs = {
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.set_ofs = 0x200,
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.clr_ofs = 0x204,
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.sta_ofs = 0x200,
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};
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static const struct mtk_gate_regs vde21_hwv_regs = {
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.set_ofs = 0x0080,
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.clr_ofs = 0x0084,
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.sta_ofs = 0x2c40,
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};
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static const struct mtk_gate_regs vde22_cg_regs = {
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.set_ofs = 0x8,
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.clr_ofs = 0xc,
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.sta_ofs = 0x8,
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};
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static const struct mtk_gate_regs vde22_hwv_regs = {
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.set_ofs = 0x0078,
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.clr_ofs = 0x007c,
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.sta_ofs = 0x2c3c,
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};
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#define GATE_HWV_VDE20(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde20_cg_regs, \
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.hwv_regs = &vde20_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VDE21(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde21_cg_regs, \
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.hwv_regs = &vde21_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VDE22(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde22_cg_regs, \
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.hwv_regs = &vde22_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE | \
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CLK_IGNORE_UNUSED, \
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}
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static const struct mtk_gate vde2_clks[] = {
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/* VDE20 */
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GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN, "vde2_vdec_cken", "vdec", 0),
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GATE_HWV_VDE20(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "vdec", 4),
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GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN_ENG, "vde2_vdec_cken_eng", "vdec", 8),
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/* VDE21 */
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GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN, "vde2_lat_cken", "vdec", 0),
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GATE_HWV_VDE21(CLK_VDE2_LAT_ACTIVE, "vde2_lat_active", "vdec", 4),
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GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN_ENG, "vde2_lat_cken_eng", "vdec", 8),
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/* VDE22 */
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GATE_HWV_VDE22(CLK_VDE2_LARB1_CKEN, "vde2_larb1_cken", "vdec", 0),
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};
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static const struct mtk_clk_desc vde2_mcd = {
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.clks = vde2_clks,
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.num_clks = ARRAY_SIZE(vde2_clks),
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.need_runtime_pm = true,
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};
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static const struct mtk_gate_regs vde10_hwv_regs = {
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.set_ofs = 0x00a0,
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.clr_ofs = 0x00a4,
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.sta_ofs = 0x2c50,
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};
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static const struct mtk_gate_regs vde11_cg_regs = {
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.set_ofs = 0x1e0,
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.clr_ofs = 0x1e0,
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.sta_ofs = 0x1e0,
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};
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static const struct mtk_gate_regs vde11_hwv_regs = {
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.set_ofs = 0x00b0,
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.clr_ofs = 0x00b4,
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.sta_ofs = 0x2c58,
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};
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static const struct mtk_gate_regs vde12_cg_regs = {
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.set_ofs = 0x1ec,
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.clr_ofs = 0x1ec,
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.sta_ofs = 0x1ec,
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};
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static const struct mtk_gate_regs vde12_hwv_regs = {
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.set_ofs = 0x00a8,
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.clr_ofs = 0x00ac,
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.sta_ofs = 0x2c54,
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};
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static const struct mtk_gate_regs vde13_cg_regs = {
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.set_ofs = 0x200,
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.clr_ofs = 0x204,
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.sta_ofs = 0x200,
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};
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static const struct mtk_gate_regs vde13_hwv_regs = {
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.set_ofs = 0x0098,
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.clr_ofs = 0x009c,
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.sta_ofs = 0x2c4c,
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};
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static const struct mtk_gate_regs vde14_hwv_regs = {
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.set_ofs = 0x0090,
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.clr_ofs = 0x0094,
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.sta_ofs = 0x2c48,
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};
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#define GATE_HWV_VDE10(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde20_cg_regs, \
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.hwv_regs = &vde10_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VDE11(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde11_cg_regs, \
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.hwv_regs = &vde11_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VDE12(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde12_cg_regs, \
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.hwv_regs = &vde12_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv, \
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.flags = CLK_OPS_PARENT_ENABLE \
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}
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#define GATE_HWV_VDE13(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde13_cg_regs, \
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.hwv_regs = &vde13_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE, \
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}
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#define GATE_HWV_VDE14(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &vde22_cg_regs, \
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.hwv_regs = &vde14_hwv_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_hwv_ops_setclr_inv,\
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.flags = CLK_OPS_PARENT_ENABLE | \
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CLK_IGNORE_UNUSED, \
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}
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static const struct mtk_gate vde1_clks[] = {
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/* VDE10 */
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GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN, "vde1_vdec_cken", "vdec", 0),
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GATE_HWV_VDE10(CLK_VDE1_VDEC_ACTIVE, "vde1_vdec_active", "vdec", 4),
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GATE_HWV_VDE10(CLK_VDE1_VDEC_CKEN_ENG, "vde1_vdec_cken_eng", "vdec", 8),
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/* VDE11 */
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GATE_HWV_VDE11(CLK_VDE1_VDEC_SOC_IPS_EN, "vde1_vdec_soc_ips_en", "vdec", 0),
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/* VDE12 */
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GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_EN, "vde1_aptv_en", "ck_tck_26m_mx9_ck", 0),
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GATE_HWV_VDE12(CLK_VDE1_VDEC_SOC_APTV_TOP_EN, "vde1_aptv_topen", "ck_tck_26m_mx9_ck", 1),
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/* VDE13 */
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GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN, "vde1_lat_cken", "vdec", 0),
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GATE_HWV_VDE13(CLK_VDE1_LAT_ACTIVE, "vde1_lat_active", "vdec", 4),
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GATE_HWV_VDE13(CLK_VDE1_LAT_CKEN_ENG, "vde1_lat_cken_eng", "vdec", 8),
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/* VDE14 */
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GATE_HWV_VDE14(CLK_VDE1_LARB1_CKEN, "vde1_larb1_cken", "vdec", 0),
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};
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static const struct mtk_clk_desc vde1_mcd = {
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.clks = vde1_clks,
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.num_clks = ARRAY_SIZE(vde1_clks),
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.need_runtime_pm = true,
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};
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static const struct of_device_id of_match_clk_mt8196_vdec[] = {
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{ .compatible = "mediatek,mt8196-vdecsys", .data = &vde2_mcd },
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{ .compatible = "mediatek,mt8196-vdecsys-soc", .data = &vde1_mcd },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_vdec);
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static struct platform_driver clk_mt8196_vdec_drv = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt8196-vdec",
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.of_match_table = of_match_clk_mt8196_vdec,
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},
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};
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module_platform_driver(clk_mt8196_vdec_drv);
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MODULE_DESCRIPTION("MediaTek MT8196 Video Decoders clocks driver");
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MODULE_LICENSE("GPL");

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