Skip to content

Commit 346878d

Browse files
sandip4nacmel
sandip4n
authored and
acmel
committed
perf vendor events amd: Add Zen 4 memory controller events
Make the jevents parser aware of the Unified Memory Controller (UMC) PMU and add events taken from Section 8.2.1 "UMC Performance Monitor Events" of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h processors. The events capture UMC command activity such as CAS, ACTIVATE, PRECHARGE etc. while the metrics derive data bus utilization and memory bandwidth out of these events. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://lore.kernel.org/r/e0d8a7e8ca8ee3e378d8029e80b456ac327d6419.1701238314.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
1 parent f2567e1 commit 346878d

3 files changed

Lines changed: 187 additions & 0 deletions

File tree

‎tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json‎

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
1+
[
2+
{
3+
"EventName": "umc_mem_clk",
4+
"PublicDescription": "Number of memory clock cycles.",
5+
"EventCode": "0x00",
6+
"PerPkg": "1",
7+
"Unit": "UMCPMC"
8+
},
9+
{
10+
"EventName": "umc_act_cmd.all",
11+
"PublicDescription": "Number of ACTIVATE commands sent.",
12+
"EventCode": "0x05",
13+
"PerPkg": "1",
14+
"Unit": "UMCPMC"
15+
},
16+
{
17+
"EventName": "umc_act_cmd.rd",
18+
"PublicDescription": "Number of ACTIVATE commands sent for reads.",
19+
"EventCode": "0x05",
20+
"RdWrMask": "0x1",
21+
"PerPkg": "1",
22+
"Unit": "UMCPMC"
23+
},
24+
{
25+
"EventName": "umc_act_cmd.wr",
26+
"PublicDescription": "Number of ACTIVATE commands sent for writes.",
27+
"EventCode": "0x05",
28+
"RdWrMask": "0x2",
29+
"PerPkg": "1",
30+
"Unit": "UMCPMC"
31+
},
32+
{
33+
"EventName": "umc_pchg_cmd.all",
34+
"PublicDescription": "Number of PRECHARGE commands sent.",
35+
"EventCode": "0x06",
36+
"PerPkg": "1",
37+
"Unit": "UMCPMC"
38+
},
39+
{
40+
"EventName": "umc_pchg_cmd.rd",
41+
"PublicDescription": "Number of PRECHARGE commands sent for reads.",
42+
"EventCode": "0x06",
43+
"RdWrMask": "0x1",
44+
"PerPkg": "1",
45+
"Unit": "UMCPMC"
46+
},
47+
{
48+
"EventName": "umc_pchg_cmd.wr",
49+
"PublicDescription": "Number of PRECHARGE commands sent for writes.",
50+
"EventCode": "0x06",
51+
"RdWrMask": "0x2",
52+
"PerPkg": "1",
53+
"Unit": "UMCPMC"
54+
},
55+
{
56+
"EventName": "umc_cas_cmd.all",
57+
"PublicDescription": "Number of CAS commands sent.",
58+
"EventCode": "0x0a",
59+
"PerPkg": "1",
60+
"Unit": "UMCPMC"
61+
},
62+
{
63+
"EventName": "umc_cas_cmd.rd",
64+
"PublicDescription": "Number of CAS commands sent for reads.",
65+
"EventCode": "0x0a",
66+
"RdWrMask": "0x1",
67+
"PerPkg": "1",
68+
"Unit": "UMCPMC"
69+
},
70+
{
71+
"EventName": "umc_cas_cmd.wr",
72+
"PublicDescription": "Number of CAS commands sent for writes.",
73+
"EventCode": "0x0a",
74+
"RdWrMask": "0x2",
75+
"PerPkg": "1",
76+
"Unit": "UMCPMC"
77+
},
78+
{
79+
"EventName": "umc_data_slot_clks.all",
80+
"PublicDescription": "Number of clocks used by the data bus.",
81+
"EventCode": "0x14",
82+
"PerPkg": "1",
83+
"Unit": "UMCPMC"
84+
},
85+
{
86+
"EventName": "umc_data_slot_clks.rd",
87+
"PublicDescription": "Number of clocks used by the data bus for reads.",
88+
"EventCode": "0x14",
89+
"RdWrMask": "0x1",
90+
"PerPkg": "1",
91+
"Unit": "UMCPMC"
92+
},
93+
{
94+
"EventName": "umc_data_slot_clks.wr",
95+
"PublicDescription": "Number of clocks used by the data bus for writes.",
96+
"EventCode": "0x14",
97+
"RdWrMask": "0x2",
98+
"PerPkg": "1",
99+
"Unit": "UMCPMC"
100+
}
101+
]

‎tools/perf/pmu-events/arch/x86/amdzen4/recommended.json‎

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,5 +330,89 @@
330330
"MetricGroup": "data_fabric",
331331
"PerPkg": "1",
332332
"ScaleUnit": "6.103515625e-5MiB"
333+
},
334+
{
335+
"MetricName": "umc_data_bus_utilization",
336+
"BriefDescription": "Memory controller data bus utilization.",
337+
"MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
338+
"MetricGroup": "memory_controller",
339+
"PerPkg": "1",
340+
"ScaleUnit": "100%"
341+
},
342+
{
343+
"MetricName": "umc_cas_cmd_rate",
344+
"BriefDescription": "Memory controller CAS command rate.",
345+
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
346+
"MetricGroup": "memory_controller",
347+
"PerPkg": "1"
348+
},
349+
{
350+
"MetricName": "umc_cas_cmd_read_ratio",
351+
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
352+
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
353+
"MetricGroup": "memory_controller",
354+
"PerPkg": "1",
355+
"ScaleUnit": "100%"
356+
},
357+
{
358+
"MetricName": "umc_cas_cmd_write_ratio",
359+
"BriefDescription": "Ratio of memory controller CAS commands for writes.",
360+
"MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
361+
"MetricGroup": "memory_controller",
362+
"PerPkg": "1",
363+
"ScaleUnit": "100%"
364+
},
365+
{
366+
"MetricName": "umc_mem_read_bandwidth",
367+
"BriefDescription": "Estimated memory read bandwidth.",
368+
"MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
369+
"MetricGroup": "memory_controller",
370+
"PerPkg": "1",
371+
"ScaleUnit": "1MB/s"
372+
},
373+
{
374+
"MetricName": "umc_mem_write_bandwidth",
375+
"BriefDescription": "Estimated memory write bandwidth.",
376+
"MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
377+
"MetricGroup": "memory_controller",
378+
"PerPkg": "1",
379+
"ScaleUnit": "1MB/s"
380+
},
381+
{
382+
"MetricName": "umc_mem_bandwidth",
383+
"BriefDescription": "Estimated combined memory bandwidth.",
384+
"MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
385+
"MetricGroup": "memory_controller",
386+
"PerPkg": "1",
387+
"ScaleUnit": "1MB/s"
388+
},
389+
{
390+
"MetricName": "umc_cas_cmd_read_ratio",
391+
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
392+
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
393+
"MetricGroup": "memory_controller",
394+
"PerPkg": "1",
395+
"ScaleUnit": "100%"
396+
},
397+
{
398+
"MetricName": "umc_cas_cmd_rate",
399+
"BriefDescription": "Memory controller CAS command rate.",
400+
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
401+
"MetricGroup": "memory_controller",
402+
"PerPkg": "1"
403+
},
404+
{
405+
"MetricName": "umc_activate_cmd_rate",
406+
"BriefDescription": "Memory controller ACTIVATE command rate.",
407+
"MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
408+
"MetricGroup": "memory_controller",
409+
"PerPkg": "1"
410+
},
411+
{
412+
"MetricName": "umc_precharge_cmd_rate",
413+
"BriefDescription": "Memory controller PRECHARGE command rate.",
414+
"MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
415+
"MetricGroup": "memory_controller",
416+
"PerPkg": "1"
333417
}
334418
]

‎tools/perf/pmu-events/jevents.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -286,6 +286,7 @@ def unit_to_pmu(unit: str) -> Optional[str]:
286286
'imx8_ddr': 'imx8_ddr',
287287
'L3PMC': 'amd_l3',
288288
'DFPMC': 'amd_df',
289+
'UMCPMC': 'amd_umc',
289290
'cpu_core': 'cpu_core',
290291
'cpu_atom': 'cpu_atom',
291292
'ali_drw': 'ali_drw',
@@ -354,6 +355,7 @@ def unit_to_pmu(unit: str) -> Optional[str]:
354355
('SampleAfterValue', 'period='),
355356
('UMask', 'umask='),
356357
('NodeType', 'type='),
358+
('RdWrMask', 'rdwrmask='),
357359
]
358360
for key, value in event_fields:
359361
if key in jd and jd[key] != '0':

0 commit comments

Comments
 (0)