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sumanku3herbertx
sumanku3
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herbertx
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crypto: qat - enable rate limiting feature for GEN6 devices
Add support for enabling rate limiting(RL) feature for QAT GEN6 by initializing the rl_data member in adf_hw_device_data structure. Implement init_num_svc_aes() for GEN6 which will populate the number of AEs associated with the RL service type. Implement adf_gen6_get_svc_slice_cnt() for GEN6 which will return the slice count that can support the RL service type. Co-developed-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: George Abraham P <george.abraham.p@intel.com> Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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3 files changed

Lines changed: 98 additions & 7 deletions

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‎Documentation/ABI/testing/sysfs-driver-qat_rl‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ Description:
3131
* rm_all: Removes all the configured SLAs.
3232
* Inputs: None
3333

34-
This attribute is only available for qat_4xxx devices.
34+
This attribute is only available for qat_4xxx and qat_6xxx devices.
3535

3636
What: /sys/bus/pci/devices/<BDF>/qat_rl/rp
3737
Date: January 2024
@@ -68,7 +68,7 @@ Description:
6868
## Write
6969
# echo 0x5 > /sys/bus/pci/devices/<BDF>/qat_rl/rp
7070

71-
This attribute is only available for qat_4xxx devices.
71+
This attribute is only available for qat_4xxx and qat_6xxx devices.
7272

7373
What: /sys/bus/pci/devices/<BDF>/qat_rl/id
7474
Date: January 2024
@@ -101,7 +101,7 @@ Description:
101101
# cat /sys/bus/pci/devices/<BDF>/qat_rl/rp
102102
0x5 ## ring pair ID 0 and ring pair ID 2
103103

104-
This attribute is only available for qat_4xxx devices.
104+
This attribute is only available for qat_4xxx and qat_6xxx devices.
105105

106106
What: /sys/bus/pci/devices/<BDF>/qat_rl/cir
107107
Date: January 2024
@@ -135,7 +135,7 @@ Description:
135135
# cat /sys/bus/pci/devices/<BDF>/qat_rl/cir
136136
500
137137

138-
This attribute is only available for qat_4xxx devices.
138+
This attribute is only available for qat_4xxx and qat_6xxx devices.
139139

140140
What: /sys/bus/pci/devices/<BDF>/qat_rl/pir
141141
Date: January 2024
@@ -169,7 +169,7 @@ Description:
169169
# cat /sys/bus/pci/devices/<BDF>/qat_rl/pir
170170
750
171171

172-
This attribute is only available for qat_4xxx devices.
172+
This attribute is only available for qat_4xxx and qat_6xxx devices.
173173

174174
What: /sys/bus/pci/devices/<BDF>/qat_rl/srv
175175
Date: January 2024
@@ -202,7 +202,7 @@ Description:
202202
# cat /sys/bus/pci/devices/<BDF>/qat_rl/srv
203203
dc
204204

205-
This attribute is only available for qat_4xxx devices.
205+
This attribute is only available for qat_4xxx and qat_6xxx devices.
206206

207207
What: /sys/bus/pci/devices/<BDF>/qat_rl/cap_rem
208208
Date: January 2024
@@ -223,4 +223,4 @@ Description:
223223
# cat /sys/bus/pci/devices/<BDF>/qat_rl/cap_rem
224224
0
225225

226-
This attribute is only available for qat_4xxx devices.
226+
This attribute is only available for qat_4xxx and qat_6xxx devices.

‎drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -524,6 +524,55 @@ static int adf_gen6_init_thd2arb_map(struct adf_accel_dev *accel_dev)
524524
return 0;
525525
}
526526

527+
static void init_num_svc_aes(struct adf_rl_hw_data *device_data)
528+
{
529+
enum adf_fw_objs obj_type, obj_iter;
530+
unsigned int svc, i, num_grp;
531+
u32 ae_mask;
532+
533+
for (svc = 0; svc < SVC_BASE_COUNT; svc++) {
534+
switch (svc) {
535+
case SVC_SYM:
536+
case SVC_ASYM:
537+
obj_type = ADF_FW_CY_OBJ;
538+
break;
539+
case SVC_DC:
540+
case SVC_DECOMP:
541+
obj_type = ADF_FW_DC_OBJ;
542+
break;
543+
}
544+
545+
num_grp = ARRAY_SIZE(adf_default_fw_config);
546+
for (i = 0; i < num_grp; i++) {
547+
obj_iter = adf_default_fw_config[i].obj;
548+
if (obj_iter == obj_type) {
549+
ae_mask = adf_default_fw_config[i].ae_mask;
550+
device_data->svc_ae_mask[svc] = hweight32(ae_mask);
551+
break;
552+
}
553+
}
554+
}
555+
}
556+
557+
static u32 adf_gen6_get_svc_slice_cnt(struct adf_accel_dev *accel_dev,
558+
enum adf_base_services svc)
559+
{
560+
struct adf_rl_hw_data *device_data = &accel_dev->hw_device->rl_data;
561+
562+
switch (svc) {
563+
case SVC_SYM:
564+
return device_data->slices.cph_cnt;
565+
case SVC_ASYM:
566+
return device_data->slices.pke_cnt;
567+
case SVC_DC:
568+
return device_data->slices.cpr_cnt + device_data->slices.dcpr_cnt;
569+
case SVC_DECOMP:
570+
return device_data->slices.dcpr_cnt;
571+
default:
572+
return 0;
573+
}
574+
}
575+
527576
static void set_vc_csr_for_bank(void __iomem *csr, u32 bank_number)
528577
{
529578
u32 value;
@@ -805,6 +854,25 @@ static int dev_config(struct adf_accel_dev *accel_dev)
805854
return ret;
806855
}
807856

857+
static void adf_gen6_init_rl_data(struct adf_rl_hw_data *rl_data)
858+
{
859+
rl_data->pciout_tb_offset = ADF_GEN6_RL_TOKEN_PCIEOUT_BUCKET_OFFSET;
860+
rl_data->pciin_tb_offset = ADF_GEN6_RL_TOKEN_PCIEIN_BUCKET_OFFSET;
861+
rl_data->r2l_offset = ADF_GEN6_RL_R2L_OFFSET;
862+
rl_data->l2c_offset = ADF_GEN6_RL_L2C_OFFSET;
863+
rl_data->c2s_offset = ADF_GEN6_RL_C2S_OFFSET;
864+
rl_data->pcie_scale_div = ADF_6XXX_RL_PCIE_SCALE_FACTOR_DIV;
865+
rl_data->pcie_scale_mul = ADF_6XXX_RL_PCIE_SCALE_FACTOR_MUL;
866+
rl_data->max_tp[SVC_ASYM] = ADF_6XXX_RL_MAX_TP_ASYM;
867+
rl_data->max_tp[SVC_SYM] = ADF_6XXX_RL_MAX_TP_SYM;
868+
rl_data->max_tp[SVC_DC] = ADF_6XXX_RL_MAX_TP_DC;
869+
rl_data->max_tp[SVC_DECOMP] = ADF_6XXX_RL_MAX_TP_DECOMP;
870+
rl_data->scan_interval = ADF_6XXX_RL_SCANS_PER_SEC;
871+
rl_data->scale_ref = ADF_6XXX_RL_SLICE_REF;
872+
873+
init_num_svc_aes(rl_data);
874+
}
875+
808876
void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
809877
{
810878
hw_data->dev_class = &adf_6xxx_class;
@@ -863,13 +931,16 @@ void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
863931
hw_data->enable_pm = enable_pm;
864932
hw_data->services_supported = services_supported;
865933
hw_data->num_rps = ADF_GEN6_ETR_MAX_BANKS;
934+
hw_data->clock_frequency = ADF_6XXX_AE_FREQ;
935+
hw_data->get_svc_slice_cnt = adf_gen6_get_svc_slice_cnt;
866936

867937
adf_gen6_init_hw_csr_ops(&hw_data->csr_ops);
868938
adf_gen6_init_pf_pfvf_ops(&hw_data->pfvf_ops);
869939
adf_gen6_init_dc_ops(&hw_data->dc_ops);
870940
adf_gen6_init_vf_mig_ops(&hw_data->vfmig_ops);
871941
adf_gen6_init_ras_ops(&hw_data->ras_ops);
872942
adf_gen6_init_tl_data(&hw_data->tl_data);
943+
adf_gen6_init_rl_data(&hw_data->rl_data);
873944
}
874945

875946
void adf_clean_hw_data_6xxx(struct adf_hw_device_data *hw_data)

‎drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,13 @@
122122
/* Number of heartbeat counter pairs */
123123
#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
124124

125+
/* Rate Limiting */
126+
#define ADF_GEN6_RL_R2L_OFFSET 0x508000
127+
#define ADF_GEN6_RL_L2C_OFFSET 0x509000
128+
#define ADF_GEN6_RL_C2S_OFFSET 0x508818
129+
#define ADF_GEN6_RL_TOKEN_PCIEIN_BUCKET_OFFSET 0x508800
130+
#define ADF_GEN6_RL_TOKEN_PCIEOUT_BUCKET_OFFSET 0x508804
131+
125132
/* Physical function fuses */
126133
#define ADF_6XXX_ACCELENGINES_MASK GENMASK(8, 0)
127134
#define ADF_6XXX_ADMIN_AE_MASK GENMASK(8, 8)
@@ -133,6 +140,19 @@
133140
#define ADF_6XXX_DC_OBJ "qat_6xxx_dc.bin"
134141
#define ADF_6XXX_ADMIN_OBJ "qat_6xxx_admin.bin"
135142

143+
/* RL constants */
144+
#define ADF_6XXX_RL_PCIE_SCALE_FACTOR_DIV 100
145+
#define ADF_6XXX_RL_PCIE_SCALE_FACTOR_MUL 102
146+
#define ADF_6XXX_RL_SCANS_PER_SEC 954
147+
#define ADF_6XXX_RL_MAX_TP_ASYM 173750UL
148+
#define ADF_6XXX_RL_MAX_TP_SYM 95000UL
149+
#define ADF_6XXX_RL_MAX_TP_DC 40000UL
150+
#define ADF_6XXX_RL_MAX_TP_DECOMP 40000UL
151+
#define ADF_6XXX_RL_SLICE_REF 1000UL
152+
153+
/* Clock frequency */
154+
#define ADF_6XXX_AE_FREQ (1000 * HZ_PER_MHZ)
155+
136156
enum icp_qat_gen6_slice_mask {
137157
ICP_ACCEL_GEN6_MASK_UCS_SLICE = BIT(0),
138158
ICP_ACCEL_GEN6_MASK_AUTH_SLICE = BIT(1),

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