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perf vendor events intel: Update sapphirerapids events to v1.17
Update to v1.17 released in: intel/perfmon#123 Add events FP_ARITH_DISPATCHED.V0, FP_ARITH_DISPATCHED.V1, FP_ARITH_DISPATCHED.V2, UNC_IIO_IOMMU0.1G_HITS, UNC_IIO_IOMMU0.2M_HITS and UNC_IIO_IOMMU0.4K_HITS. Description updates. Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Edward Baker <edward.baker@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20240104074259.653219-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎tools/perf/pmu-events/arch/x86/mapfile.csv‎

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@@ -26,7 +26,7 @@ GenuineIntel-6-1[AEF],v4,nehalemep,core
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GenuineIntel-6-2E,v4,nehalemex,core
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GenuineIntel-6-A7,v1.01,rocketlake,core
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GenuineIntel-6-2A,v19,sandybridge,core
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GenuineIntel-6-8F,v1.16,sapphirerapids,core
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GenuineIntel-6-8F,v1.17,sapphirerapids,core
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GenuineIntel-6-AF,v1.00,sierraforest,core
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GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
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GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v57,skylake,core

‎tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json‎

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@@ -23,26 +23,47 @@
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"UMask": "0x10"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is alias to FP_ARITH_DISPATCHED.V0]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is alias to FP_ARITH_DISPATCHED.V1]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
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"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is alias to FP_ARITH_DISPATCHED.V2]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.PORT_5",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias to FP_ARITH_DISPATCHED.PORT_0]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias to FP_ARITH_DISPATCHED.PORT_1]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V1",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias to FP_ARITH_DISPATCHED.PORT_5]",
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"EventCode": "0xb3",
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"EventName": "FP_ARITH_DISPATCHED.V2",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",

‎tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json‎

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"UMask": "0x1"
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},
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{
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"BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
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"BriefDescription": "Bubble cycles of BAClear (Unknown Branch).",
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"EventCode": "0xad",
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"EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES",
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"MSRIndex": "0x3F7",

‎tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json‎

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"Unit": "M3UPI"
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},
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{
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"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bouncable)",
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"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bounceable)",
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"EventCode": "0x47",
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"EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC",
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"PerPkg": "1",
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"PublicDescription": "AD Bouncable : Number of allocations into the CRS Egress",
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"PublicDescription": "AD Bounceable : Number of allocations into the CRS Egress",
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"UMask": "0x1",
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"Unit": "MDF"
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},
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"Unit": "MDF"
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},
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{
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"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bouncable)",
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"BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bounceable)",
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"EventCode": "0x47",
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"EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC",
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"PerPkg": "1",
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"PublicDescription": "BL Bouncable : Number of allocations into the CRS Egress",
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"PublicDescription": "BL Bounceable : Number of allocations into the CRS Egress",
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"UMask": "0x4",
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"Unit": "MDF"
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},

‎tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json‎

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"UMask": "0x70ff010",
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"Unit": "IIO"
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},
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{
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"BriefDescription": ": IOTLB Hits to a 1G Page",
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"EventCode": "0x40",
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"EventName": "UNC_IIO_IOMMU0.1G_HITS",
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"PerPkg": "1",
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"PortMask": "0x0000",
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"PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.",
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"UMask": "0x10",
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"Unit": "IIO"
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},
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{
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"BriefDescription": ": IOTLB Hits to a 2M Page",
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"EventCode": "0x40",
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"EventName": "UNC_IIO_IOMMU0.2M_HITS",
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"PerPkg": "1",
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"PortMask": "0x0000",
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"PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.",
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"UMask": "0x8",
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"Unit": "IIO"
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},
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{
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"BriefDescription": ": IOTLB Hits to a 4K Page",
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"EventCode": "0x40",
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"EventName": "UNC_IIO_IOMMU0.4K_HITS",
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"PerPkg": "1",
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"PortMask": "0x0000",
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"PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.",
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"UMask": "0x4",
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"Unit": "IIO"
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},
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{
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"BriefDescription": ": Context cache hits",
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"EventCode": "0x40",

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