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7 | 7 | // |
8 | 8 |
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9 | 9 | #include <linux/slab.h> |
| 10 | +#include <sound/hdaudio.h> |
| 11 | +#include <sound/hdaudio_ext.h> |
10 | 12 | #include "avs.h" |
11 | 13 | #include "messages.h" |
12 | 14 |
|
| 15 | +#define ICL_VS_LTRP_GB_ICCMAX 95 |
| 16 | + |
13 | 17 | #ifdef CONFIG_DEBUG_FS |
14 | 18 | int avs_icl_enable_logs(struct avs_dev *adev, enum avs_log_enable enable, u32 aging_period, |
15 | 19 | u32 fifo_full_period, unsigned long resource_mask, u32 *priorities) |
@@ -118,14 +122,70 @@ int avs_icl_set_d0ix(struct avs_dev *adev, bool enable) |
118 | 122 | return AVS_IPC_RET(ret); |
119 | 123 | } |
120 | 124 |
|
| 125 | +int avs_icl_load_basefw(struct avs_dev *adev, struct firmware *fw) |
| 126 | +{ |
| 127 | + struct hdac_bus *bus = &adev->base.core; |
| 128 | + struct hdac_ext_stream *host_stream; |
| 129 | + struct snd_pcm_substream substream; |
| 130 | + struct snd_dma_buffer dmab; |
| 131 | + unsigned int sd_fmt; |
| 132 | + u8 ltrp_gb; |
| 133 | + int ret; |
| 134 | + |
| 135 | + /* |
| 136 | + * ICCMAX: |
| 137 | + * |
| 138 | + * For ICL+ platforms, as per HW recommendation LTRP_GB is set to 95us |
| 139 | + * during FW load. Its original value shall be restored once load completes. |
| 140 | + * |
| 141 | + * To avoid DMI/OPIO L1 entry during the load procedure, additional CAPTURE |
| 142 | + * stream is allocated and set to run. |
| 143 | + */ |
| 144 | + |
| 145 | + memset(&substream, 0, sizeof(substream)); |
| 146 | + substream.stream = SNDRV_PCM_STREAM_CAPTURE; |
| 147 | + |
| 148 | + host_stream = snd_hdac_ext_stream_assign(bus, &substream, HDAC_EXT_STREAM_TYPE_HOST); |
| 149 | + if (!host_stream) |
| 150 | + return -EBUSY; |
| 151 | + |
| 152 | + ltrp_gb = snd_hdac_chip_readb(bus, VS_LTRP) & AZX_REG_VS_LTRP_GB_MASK; |
| 153 | + /* Carries no real data, use default format. */ |
| 154 | + sd_fmt = snd_hdac_stream_format(1, 32, 48000); |
| 155 | + |
| 156 | + ret = snd_hdac_dsp_prepare(hdac_stream(host_stream), sd_fmt, fw->size, &dmab); |
| 157 | + if (ret < 0) |
| 158 | + goto release_stream; |
| 159 | + |
| 160 | + snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ICL_VS_LTRP_GB_ICCMAX); |
| 161 | + |
| 162 | + spin_lock(&bus->reg_lock); |
| 163 | + snd_hdac_stream_start(hdac_stream(host_stream)); |
| 164 | + spin_unlock(&bus->reg_lock); |
| 165 | + |
| 166 | + ret = avs_hda_load_basefw(adev, fw); |
| 167 | + |
| 168 | + spin_lock(&bus->reg_lock); |
| 169 | + snd_hdac_stream_stop(hdac_stream(host_stream)); |
| 170 | + spin_unlock(&bus->reg_lock); |
| 171 | + |
| 172 | + snd_hdac_dsp_cleanup(hdac_stream(host_stream), &dmab); |
| 173 | + |
| 174 | +release_stream: |
| 175 | + snd_hdac_ext_stream_release(host_stream, HDAC_EXT_STREAM_TYPE_HOST); |
| 176 | + snd_hdac_chip_updateb(bus, VS_LTRP, AZX_REG_VS_LTRP_GB_MASK, ltrp_gb); |
| 177 | + |
| 178 | + return ret; |
| 179 | +} |
| 180 | + |
121 | 181 | const struct avs_dsp_ops avs_icl_dsp_ops = { |
122 | 182 | .power = avs_dsp_core_power, |
123 | 183 | .reset = avs_dsp_core_reset, |
124 | 184 | .stall = avs_dsp_core_stall, |
125 | 185 | .irq_handler = avs_irq_handler, |
126 | 186 | .irq_thread = avs_cnl_irq_thread, |
127 | 187 | .int_control = avs_dsp_interrupt_control, |
128 | | - .load_basefw = avs_hda_load_basefw, |
| 188 | + .load_basefw = avs_icl_load_basefw, |
129 | 189 | .load_lib = avs_hda_load_library, |
130 | 190 | .transfer_mods = avs_hda_transfer_modules, |
131 | 191 | .log_buffer_offset = avs_icl_log_buffer_offset, |
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