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jernejskwens
jernejsk
authored and
wens
committed
drm/sun4i: layers: Make regmap for layers configurable
Till DE33, there were no reason to decouple registers from mixer. However, with future new plane driver, this will be necessary. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-21-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
1 parent f54c353 commit 37aba59

8 files changed

Lines changed: 50 additions & 41 deletions

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‎drivers/gpu/drm/sun4i/sun8i_mixer.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,9 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
332332
else
333333
type = DRM_PLANE_TYPE_OVERLAY;
334334

335-
layer = sun8i_vi_layer_init_one(drm, mixer, type, i, plane_cnt);
335+
layer = sun8i_vi_layer_init_one(drm, mixer, type,
336+
mixer->engine.regs, i,
337+
plane_cnt);
336338
if (IS_ERR(layer)) {
337339
dev_err(drm->dev,
338340
"Couldn't initialize overlay plane\n");
@@ -351,7 +353,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
351353
else
352354
type = DRM_PLANE_TYPE_OVERLAY;
353355

354-
layer = sun8i_ui_layer_init_one(drm, mixer, type, index,
356+
layer = sun8i_ui_layer_init_one(drm, mixer, type,
357+
mixer->engine.regs, index,
355358
plane_cnt);
356359
if (IS_ERR(layer)) {
357360
dev_err(drm->dev, "Couldn't initialize %s plane\n",

‎drivers/gpu/drm/sun4i/sun8i_mixer.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,7 @@ struct sun8i_layer {
214214
int type;
215215
int channel;
216216
int overlay;
217+
struct regmap *regs;
217218
};
218219

219220
static inline struct sun8i_layer *

‎drivers/gpu/drm/sun4i/sun8i_ui_layer.c‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ static void sun8i_ui_layer_update_attributes(struct sun8i_layer *layer,
5454
val |= hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
5555
val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
5656

57-
regmap_write(mixer->engine.regs,
57+
regmap_write(layer->regs,
5858
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), val);
5959
}
6060

@@ -88,10 +88,10 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer,
8888
DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n",
8989
state->src.x1 >> 16, state->src.y1 >> 16);
9090
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
91-
regmap_write(mixer->engine.regs,
91+
regmap_write(layer->regs,
9292
SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, layer->overlay),
9393
insize);
94-
regmap_write(mixer->engine.regs,
94+
regmap_write(layer->regs,
9595
SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base),
9696
insize);
9797

@@ -150,13 +150,13 @@ static void sun8i_ui_layer_update_buffer(struct sun8i_layer *layer,
150150

151151
/* Set the line width */
152152
DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]);
153-
regmap_write(mixer->engine.regs,
153+
regmap_write(layer->regs,
154154
SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, layer->overlay),
155155
fb->pitches[0]);
156156

157157
DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr);
158158

159-
regmap_write(mixer->engine.regs,
159+
regmap_write(layer->regs,
160160
SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, layer->overlay),
161161
lower_32_bits(dma_addr));
162162
}
@@ -264,6 +264,7 @@ static const uint64_t sun8i_layer_modifiers[] = {
264264
struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
265265
struct sun8i_mixer *mixer,
266266
enum drm_plane_type type,
267+
struct regmap *regs,
267268
int index,
268269
int plane_cnt)
269270
{
@@ -278,6 +279,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
278279
layer->type = SUN8I_LAYER_TYPE_UI;
279280
layer->channel = index;
280281
layer->overlay = 0;
282+
layer->regs = regs;
281283

282284
/* possible crtcs are set later */
283285
ret = drm_universal_plane_init(drm, &layer->plane, 0,

‎drivers/gpu/drm/sun4i/sun8i_ui_layer.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ struct sun8i_layer;
5252
struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
5353
struct sun8i_mixer *mixer,
5454
enum drm_plane_type type,
55+
struct regmap *regs,
5556
int index,
5657
int plane_cnt);
5758
#endif /* _SUN8I_UI_LAYER_H_ */

‎drivers/gpu/drm/sun4i/sun8i_ui_scaler.c‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ void sun8i_ui_scaler_enable(struct sun8i_layer *layer, bool enable)
143143
else
144144
val = 0;
145145

146-
regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val);
146+
regmap_write(layer->regs, SUN8I_SCALER_GSU_CTRL(base), val);
147147
}
148148

149149
void sun8i_ui_scaler_setup(struct sun8i_layer *layer,
@@ -168,22 +168,22 @@ void sun8i_ui_scaler_setup(struct sun8i_layer *layer,
168168
insize = SUN8I_UI_SCALER_SIZE(src_w, src_h);
169169
outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h);
170170

171-
regmap_write(mixer->engine.regs,
171+
regmap_write(layer->regs,
172172
SUN8I_SCALER_GSU_OUTSIZE(base), outsize);
173-
regmap_write(mixer->engine.regs,
173+
regmap_write(layer->regs,
174174
SUN8I_SCALER_GSU_INSIZE(base), insize);
175-
regmap_write(mixer->engine.regs,
175+
regmap_write(layer->regs,
176176
SUN8I_SCALER_GSU_HSTEP(base), hscale);
177-
regmap_write(mixer->engine.regs,
177+
regmap_write(layer->regs,
178178
SUN8I_SCALER_GSU_VSTEP(base), vscale);
179-
regmap_write(mixer->engine.regs,
179+
regmap_write(layer->regs,
180180
SUN8I_SCALER_GSU_HPHASE(base), hphase);
181-
regmap_write(mixer->engine.regs,
181+
regmap_write(layer->regs,
182182
SUN8I_SCALER_GSU_VPHASE(base), vphase);
183183
offset = sun8i_ui_scaler_coef_index(hscale) *
184184
SUN8I_UI_SCALER_COEFF_COUNT;
185185
for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++)
186-
regmap_write(mixer->engine.regs,
186+
regmap_write(layer->regs,
187187
SUN8I_SCALER_GSU_HCOEFF(base, i),
188188
lan2coefftab16[offset + i]);
189189
}

‎drivers/gpu/drm/sun4i/sun8i_vi_layer.c‎

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,12 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer,
5050
SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL :
5151
SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED;
5252
} else if (mixer->cfg->vi_num == 1) {
53-
regmap_write(mixer->engine.regs,
53+
regmap_write(layer->regs,
5454
SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG,
5555
SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8));
5656
}
5757

58-
regmap_write(mixer->engine.regs,
58+
regmap_write(layer->regs,
5959
SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val);
6060
}
6161

@@ -113,10 +113,10 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
113113
(state->src.x1 >> 16) & ~(format->hsub - 1),
114114
(state->src.y1 >> 16) & ~(format->vsub - 1));
115115
DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h);
116-
regmap_write(mixer->engine.regs,
116+
regmap_write(layer->regs,
117117
SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, layer->overlay),
118118
insize);
119-
regmap_write(mixer->engine.regs,
119+
regmap_write(layer->regs,
120120
SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base),
121121
insize);
122122

@@ -171,19 +171,19 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer,
171171
sun8i_vi_scaler_enable(layer, false);
172172
}
173173

174-
regmap_write(mixer->engine.regs,
174+
regmap_write(layer->regs,
175175
SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base),
176176
SUN8I_MIXER_CHAN_VI_DS_N(hn) |
177177
SUN8I_MIXER_CHAN_VI_DS_M(hm));
178-
regmap_write(mixer->engine.regs,
178+
regmap_write(layer->regs,
179179
SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base),
180180
SUN8I_MIXER_CHAN_VI_DS_N(hn) |
181181
SUN8I_MIXER_CHAN_VI_DS_M(hm));
182-
regmap_write(mixer->engine.regs,
182+
regmap_write(layer->regs,
183183
SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base),
184184
SUN8I_MIXER_CHAN_VI_DS_N(vn) |
185185
SUN8I_MIXER_CHAN_VI_DS_M(vm));
186-
regmap_write(mixer->engine.regs,
186+
regmap_write(layer->regs,
187187
SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base),
188188
SUN8I_MIXER_CHAN_VI_DS_N(vn) |
189189
SUN8I_MIXER_CHAN_VI_DS_M(vm));
@@ -232,15 +232,15 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer,
232232
/* Set the line width */
233233
DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n",
234234
i + 1, fb->pitches[i]);
235-
regmap_write(mixer->engine.regs,
235+
regmap_write(layer->regs,
236236
SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base,
237237
layer->overlay, i),
238238
fb->pitches[i]);
239239

240240
DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n",
241241
i + 1, &dma_addr);
242242

243-
regmap_write(mixer->engine.regs,
243+
regmap_write(layer->regs,
244244
SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base,
245245
layer->overlay, i),
246246
lower_32_bits(dma_addr));
@@ -410,6 +410,7 @@ static const uint64_t sun8i_layer_modifiers[] = {
410410
struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
411411
struct sun8i_mixer *mixer,
412412
enum drm_plane_type type,
413+
struct regmap *regs,
413414
int index,
414415
int plane_cnt)
415416
{
@@ -427,6 +428,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
427428
layer->type = SUN8I_LAYER_TYPE_VI;
428429
layer->channel = index;
429430
layer->overlay = 0;
431+
layer->regs = regs;
430432

431433
if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) {
432434
formats = sun8i_vi_layer_de3_formats;

‎drivers/gpu/drm/sun4i/sun8i_vi_layer.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ struct sun8i_layer;
5757
struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
5858
struct sun8i_mixer *mixer,
5959
enum drm_plane_type type,
60+
struct regmap *regs,
6061
int index,
6162
int plane_cnt);
6263
#endif /* _SUN8I_VI_LAYER_H_ */

‎drivers/gpu/drm/sun4i/sun8i_vi_scaler.c‎

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -911,18 +911,17 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
911911

912912
void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable)
913913
{
914-
struct sun8i_mixer *mixer = layer->mixer;
915914
u32 val, base;
916915

917-
base = sun8i_vi_scaler_base(mixer, layer->channel);
916+
base = sun8i_vi_scaler_base(layer->mixer, layer->channel);
918917

919918
if (enable)
920919
val = SUN8I_SCALER_VSU_CTRL_EN |
921920
SUN8I_SCALER_VSU_CTRL_COEFF_RDY;
922921
else
923922
val = 0;
924923

925-
regmap_write(mixer->engine.regs,
924+
regmap_write(layer->regs,
926925
SUN8I_SCALER_VSU_CTRL(base), val);
927926
}
928927

@@ -968,36 +967,36 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer,
968967
else
969968
val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL;
970969

971-
regmap_write(mixer->engine.regs,
970+
regmap_write(layer->regs,
972971
SUN50I_SCALER_VSU_SCALE_MODE(base), val);
973972
}
974973

975-
regmap_write(mixer->engine.regs,
974+
regmap_write(layer->regs,
976975
SUN8I_SCALER_VSU_OUTSIZE(base), outsize);
977-
regmap_write(mixer->engine.regs,
976+
regmap_write(layer->regs,
978977
SUN8I_SCALER_VSU_YINSIZE(base), insize);
979-
regmap_write(mixer->engine.regs,
978+
regmap_write(layer->regs,
980979
SUN8I_SCALER_VSU_YHSTEP(base), hscale);
981-
regmap_write(mixer->engine.regs,
980+
regmap_write(layer->regs,
982981
SUN8I_SCALER_VSU_YVSTEP(base), vscale);
983-
regmap_write(mixer->engine.regs,
982+
regmap_write(layer->regs,
984983
SUN8I_SCALER_VSU_YHPHASE(base), hphase);
985-
regmap_write(mixer->engine.regs,
984+
regmap_write(layer->regs,
986985
SUN8I_SCALER_VSU_YVPHASE(base), vphase);
987-
regmap_write(mixer->engine.regs,
986+
regmap_write(layer->regs,
988987
SUN8I_SCALER_VSU_CINSIZE(base),
989988
SUN8I_VI_SCALER_SIZE(src_w / format->hsub,
990989
src_h / format->vsub));
991-
regmap_write(mixer->engine.regs,
990+
regmap_write(layer->regs,
992991
SUN8I_SCALER_VSU_CHSTEP(base),
993992
hscale / format->hsub);
994-
regmap_write(mixer->engine.regs,
993+
regmap_write(layer->regs,
995994
SUN8I_SCALER_VSU_CVSTEP(base),
996995
vscale / format->vsub);
997-
regmap_write(mixer->engine.regs,
996+
regmap_write(layer->regs,
998997
SUN8I_SCALER_VSU_CHPHASE(base), chphase);
999-
regmap_write(mixer->engine.regs,
998+
regmap_write(layer->regs,
1000999
SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
1001-
sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
1000+
sun8i_vi_scaler_set_coeff(layer->regs, base,
10021001
hscale, vscale, format);
10031002
}

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