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Hans Zhangbjorn-helgaas
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PCI: Clean up __pci_find_next_cap_ttl() readability
Refactor the __pci_find_next_cap_ttl() to improve code clarity: - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. - Use ALIGN_DOWN() for position alignment instead of manual bitmask. - Extract PCI capability fields via FIELD_GET() with standardized masks. - Add necessary headers (linux/align.h). No functional changes intended. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Niklas Schnelle <schnelle@linux.ibm.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20250813144529.303548-2-18255117159@163.com
1 parent 8f5ae30 commit 37d1ade

2 files changed

Lines changed: 8 additions & 4 deletions

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drivers/pci/pci.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
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*/
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1111
#include <linux/acpi.h>
12+
#include <linux/align.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/dmi.h>
@@ -432,17 +433,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
432433
pci_bus_read_config_byte(bus, devfn, pos, &pos);
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434435
while ((*ttl)--) {
435-
if (pos < 0x40)
436+
if (pos < PCI_STD_HEADER_SIZEOF)
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break;
437-
pos &= ~3;
438+
pos = ALIGN_DOWN(pos, 4);
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pci_bus_read_config_word(bus, devfn, pos, &ent);
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440-
id = ent & 0xff;
441+
id = FIELD_GET(PCI_CAP_ID_MASK, ent);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
445-
pos = (ent >> 8);
446+
pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent);
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}
447448
return 0;
448449
}

include/uapi/linux/pci_regs.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,9 @@
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/* Capability lists */
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210+
#define PCI_CAP_ID_MASK 0x00ff /* Capability ID mask */
211+
#define PCI_CAP_LIST_NEXT_MASK 0xff00 /* Next Capability Pointer mask */
212+
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#define PCI_CAP_LIST_ID 0 /* Capability ID */
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#define PCI_CAP_ID_PM 0x01 /* Power Management */
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#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */

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