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Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
* clk-samsung: clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units clk: samsung: exynos990: Add missing USB clock registers to HSI0 clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC clk: samsung: Add clock PLL support for ARTPEC-8 SoC dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: pll: convert from round_rate() to determine_rate() clk: samsung: cpu: convert from round_rate() to determine_rate() clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block dt-bindings: clock: Add CAM_CSI clock macro for FSD * clk-tegra: clk: tegra: dfll: Add CVB tables for Tegra114 clk: tegra: Add DFLL DVCO reset control for Tegra114 dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C * clk-amlogic: clk: amlogic: fix recent code refactoring clk: amlogic: c3-peripherals: use helper for basic composite clocks clk: amlogic: align s4 and c3 pwm clock descriptions clk: amlogic: add composite clock helpers clk: amlogic: use the common pclk definition clk: amlogic: introduce a common pclk definition clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks clk: amlogic: move PCLK definition to clkc-utils clk: amlogic: aoclk: use clkc-utils syscon probe clk: amlogic: use probe helper in mmio based controllers clk: amlogic: add probe helper for mmio based controllers clk: amlogic: drop meson-clkcee clk: amlogic: naming consistency alignment
4 parents ec73364 + 823699c + ccd74be + 7e2e4e3 commit 3aae991

48 files changed

Lines changed: 7669 additions & 6136 deletions

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‎Documentation/devicetree/bindings/arm/tegra.yaml‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,8 +36,12 @@ properties:
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- toradex,colibri_t20-iris
3737
- const: toradex,colibri_t20
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- const: nvidia,tegra20
39-
- items:
40-
- const: asus,tf101
39+
- description: ASUS Transformers T20 Device family
40+
items:
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- enum:
42+
- asus,sl101
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- asus,tf101
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- asus,tf101g
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- const: nvidia,tegra20
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- items:
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- const: acer,picasso
@@ -174,6 +178,10 @@ properties:
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- const: google,nyan-big
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- const: google,nyan
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- const: nvidia,tegra124
181+
- description: Xiaomi Mi Pad (A0101)
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items:
183+
- const: xiaomi,mocha
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- const: nvidia,tegra124
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- items:
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- enum:
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- nvidia,darcy

‎Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,213 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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7+
title: Axis ARTPEC-8 SoC clock controller
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9+
maintainers:
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- Jesper Nilsson <jesper.nilsson@axis.com>
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description: |
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ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
14+
units, generating clocks for different domains. Those CMU units are modeled
15+
as separate device tree nodes, and might depend on each other.
16+
The root clock in that root tree is an external clock: OSCCLK (25 MHz).
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This external clock must be defined as a fixed-rate clock in dts.
18+
19+
CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
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dividers; all other clocks of function blocks (other CMUs) are usually
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derived from CMU_CMU.
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Each clock is assigned an identifier and client nodes can use this identifier
24+
to specify the clock which they consume. All clocks available for usage
25+
in clock consumer nodes are defined as preprocessor macros in
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'include/dt-bindings/clock/axis,artpec8-clk.h' header.
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properties:
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compatible:
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enum:
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- axis,artpec8-cmu-cmu
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- axis,artpec8-cmu-bus
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- axis,artpec8-cmu-core
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- axis,artpec8-cmu-cpucl
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- axis,artpec8-cmu-fsys
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- axis,artpec8-cmu-imem
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- axis,artpec8-cmu-peri
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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"#clock-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#clock-cells"
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allOf:
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-cmu
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66+
then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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clock-names:
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items:
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- const: fin_pll
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-bus
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81+
then:
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properties:
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clocks:
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items:
85+
- description: External reference clock (25 MHz)
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- description: CMU_BUS BUS clock (from CMU_CMU)
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- description: CMU_BUS DLP clock (from CMU_CMU)
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clock-names:
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items:
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- const: fin_pll
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- const: bus
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- const: dlp
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- if:
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properties:
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compatible:
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const: axis,artpec8-cmu-core
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100+
then:
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properties:
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clocks:
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items:
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- description: External reference clock (25 MHz)
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- description: CMU_CORE main clock (from CMU_CMU)
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- description: CMU_CORE DLP clock (from CMU_CMU)
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108+
clock-names:
109+
items:
110+
- const: fin_pll
111+
- const: main
112+
- const: dlp
113+
114+
- if:
115+
properties:
116+
compatible:
117+
const: axis,artpec8-cmu-cpucl
118+
119+
then:
120+
properties:
121+
clocks:
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items:
123+
- description: External reference clock (25 MHz)
124+
- description: CMU_CPUCL switch clock (from CMU_CMU)
125+
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clock-names:
127+
items:
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- const: fin_pll
129+
- const: switch
130+
131+
- if:
132+
properties:
133+
compatible:
134+
const: axis,artpec8-cmu-fsys
135+
136+
then:
137+
properties:
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clocks:
139+
items:
140+
- description: External reference clock (25 MHz)
141+
- description: CMU_FSYS SCAN0 clock (from CMU_CMU)
142+
- description: CMU_FSYS SCAN1 clock (from CMU_CMU)
143+
- description: CMU_FSYS BUS clock (from CMU_CMU)
144+
- description: CMU_FSYS IP clock (from CMU_CMU)
145+
146+
clock-names:
147+
items:
148+
- const: fin_pll
149+
- const: scan0
150+
- const: scan1
151+
- const: bus
152+
- const: ip
153+
154+
- if:
155+
properties:
156+
compatible:
157+
const: axis,artpec8-cmu-imem
158+
159+
then:
160+
properties:
161+
clocks:
162+
items:
163+
- description: External reference clock (25 MHz)
164+
- description: CMU_IMEM ACLK clock (from CMU_CMU)
165+
- description: CMU_IMEM JPEG clock (from CMU_CMU)
166+
167+
clock-names:
168+
items:
169+
- const: fin_pll
170+
- const: aclk
171+
- const: jpeg
172+
173+
- if:
174+
properties:
175+
compatible:
176+
const: axis,artpec8-cmu-peri
177+
178+
then:
179+
properties:
180+
clocks:
181+
items:
182+
- description: External reference clock (25 MHz)
183+
- description: CMU_PERI IP clock (from CMU_CMU)
184+
- description: CMU_PERI AUDIO clock (from CMU_CMU)
185+
- description: CMU_PERI DISP clock (from CMU_CMU)
186+
187+
clock-names:
188+
items:
189+
- const: fin_pll
190+
- const: ip
191+
- const: audio
192+
- const: disp
193+
194+
additionalProperties: false
195+
196+
examples:
197+
# Clock controller node for CMU_FSYS
198+
- |
199+
#include <dt-bindings/clock/axis,artpec8-clk.h>
200+
201+
cmu_fsys: clock-controller@16c10000 {
202+
compatible = "axis,artpec8-cmu-fsys";
203+
reg = <0x16c10000 0x4000>;
204+
#clock-cells = <1>;
205+
clocks = <&fin_pll>,
206+
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,
207+
<&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,
208+
<&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,
209+
<&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;
210+
clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";
211+
};
212+
213+
...

‎Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@ description: |
3030
properties:
3131
compatible:
3232
enum:
33+
- samsung,exynos990-cmu-peric1
34+
- samsung,exynos990-cmu-peric0
3335
- samsung,exynos990-cmu-hsi0
3436
- samsung,exynos990-cmu-peris
3537
- samsung,exynos990-cmu-top
@@ -56,6 +58,28 @@ required:
5658
- reg
5759

5860
allOf:
61+
- if:
62+
properties:
63+
compatible:
64+
contains:
65+
enum:
66+
- samsung,exynos990-cmu-peric1
67+
- samsung,exynos990-cmu-peric0
68+
69+
then:
70+
properties:
71+
clocks:
72+
items:
73+
- description: External reference clock (26 MHz)
74+
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
75+
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
76+
77+
clock-names:
78+
items:
79+
- const: oscclk
80+
- const: bus
81+
- const: ip
82+
5983
- if:
6084
properties:
6185
compatible:

‎Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ description: |
2525
properties:
2626
compatible:
2727
enum:
28+
- samsung,s2mpg10-clk
2829
- samsung,s2mps11-clk
2930
- samsung,s2mps13-clk # S2MPS13 and S2MPS15
3031
- samsung,s2mps14-clk

‎Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -70,9 +70,6 @@ properties:
7070
ranges:
7171
maxItems: 1
7272

73-
avdd-dsi-csi-supply:
74-
description: DSI/CSI power supply. Must supply 1.2 V.
75-
7673
vip:
7774
$ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
7875

‎Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,9 @@ properties:
3737
- const: cile
3838
- const: csi_tpg
3939

40+
avdd-dsi-csi-supply:
41+
description: DSI/CSI power supply. Must supply 1.2 V.
42+
4043
power-domains:
4144
maxItems: 1
4245

‎Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,12 @@ properties:
8080
support for 64 KiB transactions whereas earlier chips supported no
8181
more than 4 KiB per transactions.
8282
const: nvidia,tegra194-i2c
83+
- description:
84+
Tegra264 has 17 generic I2C controllers, two of which are in the AON
85+
(always-on) partition of the SoC. In addition to the features from
86+
Tegra194, a SW mutex register is added to support use of the same I2C
87+
instance across multiple firmwares.
88+
const: nvidia,tegra264-i2c
8389

8490
reg:
8591
maxItems: 1
@@ -186,6 +192,7 @@ allOf:
186192
contains:
187193
enum:
188194
- nvidia,tegra194-i2c
195+
- nvidia,tegra264-i2c
189196
then:
190197
required:
191198
- resets

‎drivers/clk/clk-s2mps11.c‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include <linux/regmap.h>
1212
#include <linux/clk-provider.h>
1313
#include <linux/platform_device.h>
14+
#include <linux/mfd/samsung/s2mpg10.h>
1415
#include <linux/mfd/samsung/s2mps11.h>
1516
#include <linux/mfd/samsung/s2mps13.h>
1617
#include <linux/mfd/samsung/s2mps14.h>
@@ -140,6 +141,9 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
140141
clk_data->num = S2MPS11_CLKS_NUM;
141142

142143
switch (hwid) {
144+
case S2MPG10:
145+
s2mps11_reg = S2MPG10_PMIC_RTCBUF;
146+
break;
143147
case S2MPS11X:
144148
s2mps11_reg = S2MPS11_REG_RTC_CTRL;
145149
break;
@@ -221,6 +225,7 @@ static void s2mps11_clk_remove(struct platform_device *pdev)
221225
}
222226

223227
static const struct platform_device_id s2mps11_clk_id[] = {
228+
{ "s2mpg10-clk", S2MPG10},
224229
{ "s2mps11-clk", S2MPS11X},
225230
{ "s2mps13-clk", S2MPS13X},
226231
{ "s2mps14-clk", S2MPS14X},
@@ -241,6 +246,9 @@ MODULE_DEVICE_TABLE(platform, s2mps11_clk_id);
241246
*/
242247
static const struct of_device_id s2mps11_dt_match[] __used = {
243248
{
249+
.compatible = "samsung,s2mpg10-clk",
250+
.data = (void *)S2MPG10,
251+
}, {
244252
.compatible = "samsung,s2mps11-clk",
245253
.data = (void *)S2MPS11X,
246254
}, {

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