@@ -3041,59 +3041,113 @@ static int btusb_mtk_subsys_reset(struct hci_dev *hdev, u32 dev_id)
30413041 int err ;
30423042
30433043 if (dev_id == 0x7922 ) {
3044- btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3044+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3045+ if (err < 0 )
3046+ return err ;
30453047 val |= 0x00002020 ;
3046- btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , val );
3047- btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , 0x00010001 );
3048- btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3048+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , val );
3049+ if (err < 0 )
3050+ return err ;
3051+ err = btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , 0x00010001 );
3052+ if (err < 0 )
3053+ return err ;
3054+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3055+ if (err < 0 )
3056+ return err ;
30493057 val |= BIT (0 );
3050- btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , val );
3058+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , val );
3059+ if (err < 0 )
3060+ return err ;
30513061 msleep (100 );
30523062 } else if (dev_id == 0x7925 ) {
3053- btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3063+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3064+ if (err < 0 )
3065+ return err ;
30543066 val |= (1 << 5 );
3055- btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3056- btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3067+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3068+ if (err < 0 )
3069+ return err ;
3070+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3071+ if (err < 0 )
3072+ return err ;
30573073 val &= 0xFFFF00FF ;
3074+ if (err < 0 )
3075+ return err ;
30583076 val |= (1 << 13 );
3059- btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3060- btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , 0x00010001 );
3061- btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3077+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3078+ if (err < 0 )
3079+ return err ;
3080+ err = btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , 0x00010001 );
3081+ if (err < 0 )
3082+ return err ;
3083+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_RESET_REG_CONNV3 , & val );
3084+ if (err < 0 )
3085+ return err ;
30623086 val |= (1 << 0 );
3063- btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3064- btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3065- btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT , & val );
3066- btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT1 , 0x000000FF );
3067- btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT1 , & val );
3087+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_RESET_REG_CONNV3 , val );
3088+ if (err < 0 )
3089+ return err ;
3090+ err = btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3091+ if (err < 0 )
3092+ return err ;
3093+ err = btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT , & val );
3094+ if (err < 0 )
3095+ return err ;
3096+ err = btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT1 , 0x000000FF );
3097+ if (err < 0 )
3098+ return err ;
3099+ err = btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT1 , & val );
3100+ if (err < 0 )
3101+ return err ;
30683102 msleep (100 );
30693103 } else {
30703104 /* It's Device EndPoint Reset Option Register */
30713105 bt_dev_dbg (hdev , "Initiating reset mechanism via uhw" );
3072- btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , MTK_EP_RST_IN_OUT_OPT );
3073- btusb_mtk_uhw_reg_read (data , MTK_BT_WDT_STATUS , & val );
3074-
3106+ err = btusb_mtk_uhw_reg_write (data , MTK_EP_RST_OPT , MTK_EP_RST_IN_OUT_OPT );
3107+ if (err < 0 )
3108+ return err ;
3109+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_WDT_STATUS , & val );
3110+ if (err < 0 )
3111+ return err ;
30753112 /* Reset the bluetooth chip via USB interface. */
3076- btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , 1 );
3077- btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3078- btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT , & val );
3079- btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT1 , 0x000000FF );
3080- btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT1 , & val );
3113+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , 1 );
3114+ if (err < 0 )
3115+ return err ;
3116+ err = btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3117+ if (err < 0 )
3118+ return err ;
3119+ err = btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT , & val );
3120+ if (err < 0 )
3121+ return err ;
3122+ err = btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT1 , 0x000000FF );
3123+ if (err < 0 )
3124+ return err ;
3125+ err = btusb_mtk_uhw_reg_read (data , MTK_UDMA_INT_STA_BT1 , & val );
3126+ if (err < 0 )
3127+ return err ;
30813128 /* MT7921 need to delay 20ms between toggle reset bit */
30823129 msleep (20 );
3083- btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , 0 );
3084- btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3130+ err = btusb_mtk_uhw_reg_write (data , MTK_BT_SUBSYS_RST , 0 );
3131+ if (err < 0 )
3132+ return err ;
3133+ err = btusb_mtk_uhw_reg_read (data , MTK_BT_SUBSYS_RST , & val );
3134+ if (err < 0 )
3135+ return err ;
30853136 }
30863137
30873138 err = readx_poll_timeout (btusb_mtk_reset_done , hdev , val ,
30883139 val & MTK_BT_RST_DONE , 20000 , 1000000 );
30893140 if (err < 0 )
30903141 bt_dev_err (hdev , "Reset timeout" );
30913142
3092- if (dev_id == 0x7922 )
3093- btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3143+ if (dev_id == 0x7922 ) {
3144+ err = btusb_mtk_uhw_reg_write (data , MTK_UDMA_INT_STA_BT , 0x000000FF );
3145+ if (err < 0 )
3146+ return err ;
3147+ }
30943148
3095- btusb_mtk_id_get (data , 0x70010200 , & val );
3096- if (!val )
3149+ err = btusb_mtk_id_get (data , 0x70010200 , & val );
3150+ if (err < 0 || !val )
30973151 bt_dev_err (hdev , "Can't get device id, subsys reset fail." );
30983152
30993153 return err ;
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