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regulator: mt6358: Add supply names for MT6358 regulators
The DT bindings for MT6358 regulator now defines the supply names for the PMIC. Add support for them by adding .supply_name field settings for each regulator. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230928085537.3246669-8-wenst@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
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Lines changed: 51 additions & 55 deletions

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‎drivers/regulator/mt6358-regulator.c‎

Lines changed: 51 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -33,12 +33,13 @@ struct mt6358_regulator_info {
3333

3434
#define to_regulator_info(x) container_of((x), struct mt6358_regulator_info, desc)
3535

36-
#define MT6358_BUCK(match, vreg, min, max, step, \
37-
vosel_mask, _da_vsel_reg, _da_vsel_mask, \
38-
_modeset_reg, _modeset_shift) \
36+
#define MT6358_BUCK(match, vreg, supply, min, max, step, \
37+
vosel_mask, _da_vsel_reg, _da_vsel_mask, \
38+
_modeset_reg, _modeset_shift) \
3939
[MT6358_ID_##vreg] = { \
4040
.desc = { \
4141
.name = #vreg, \
42+
.supply_name = supply, \
4243
.of_match = of_match_ptr(match), \
4344
.ops = &mt6358_volt_range_ops, \
4445
.type = REGULATOR_VOLTAGE, \
@@ -61,10 +62,11 @@ struct mt6358_regulator_info {
6162
.modeset_mask = BIT(_modeset_shift), \
6263
}
6364

64-
#define MT6358_LDO(match, vreg, volt_ranges, enreg, enbit, vosel, vosel_mask) \
65+
#define MT6358_LDO(match, vreg, supply, volt_ranges, enreg, enbit, vosel, vosel_mask) \
6566
[MT6358_ID_##vreg] = { \
6667
.desc = { \
6768
.name = #vreg, \
69+
.supply_name = supply, \
6870
.of_match = of_match_ptr(match), \
6971
.ops = &mt6358_volt_table_ops, \
7072
.type = REGULATOR_VOLTAGE, \
@@ -85,12 +87,12 @@ struct mt6358_regulator_info {
8587
.qi = BIT(15), \
8688
}
8789

88-
#define MT6358_LDO1(match, vreg, min, max, step, \
89-
_da_vsel_reg, _da_vsel_mask, \
90-
vosel, vosel_mask) \
90+
#define MT6358_LDO1(match, vreg, supply, min, max, step, \
91+
_da_vsel_reg, _da_vsel_mask, vosel, vosel_mask) \
9192
[MT6358_ID_##vreg] = { \
9293
.desc = { \
9394
.name = #vreg, \
95+
.supply_name = supply, \
9496
.of_match = of_match_ptr(match), \
9597
.ops = &mt6358_volt_range_ops, \
9698
.type = REGULATOR_VOLTAGE, \
@@ -110,11 +112,11 @@ struct mt6358_regulator_info {
110112
.qi = BIT(0), \
111113
}
112114

113-
#define MT6358_REG_FIXED(match, vreg, \
114-
enreg, enbit, volt) \
115+
#define MT6358_REG_FIXED(match, vreg, supply, enreg, enbit, volt) \
115116
[MT6358_ID_##vreg] = { \
116117
.desc = { \
117118
.name = #vreg, \
119+
.supply_name = supply, \
118120
.of_match = of_match_ptr(match), \
119121
.ops = &mt6358_volt_fixed_ops, \
120122
.type = REGULATOR_VOLTAGE, \
@@ -451,79 +453,73 @@ static const struct regulator_ops mt6358_volt_fixed_ops = {
451453

452454
/* The array is indexed by id(MT6358_ID_XXX) */
453455
static const struct mt6358_regulator_info mt6358_regulators[] = {
454-
MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
456+
MT6358_BUCK("buck_vdram1", VDRAM1, "vsys-vdram1", 500000, 2087500, 12500,
455457
0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
456-
MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
458+
MT6358_BUCK("buck_vcore", VCORE, "vsys-vcore", 500000, 1293750, 6250,
457459
0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
458-
MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
460+
MT6358_BUCK("buck_vpa", VPA, "vsys-vpa", 500000, 3650000, 50000,
459461
0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
460-
MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
462+
MT6358_BUCK("buck_vproc11", VPROC11, "vsys-vproc11", 500000, 1293750, 6250,
461463
0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
462-
MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
464+
MT6358_BUCK("buck_vproc12", VPROC12, "vsys-vproc12", 500000, 1293750, 6250,
463465
0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
464-
MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
466+
MT6358_BUCK("buck_vgpu", VGPU, "vsys-vgpu", 500000, 1293750, 6250,
465467
0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
466-
MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
468+
MT6358_BUCK("buck_vs2", VS2, "vsys-vs2", 500000, 2087500, 12500,
467469
0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
468-
MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
470+
MT6358_BUCK("buck_vmodem", VMODEM, "vsys-vmodem", 500000, 1293750, 6250,
469471
0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
470-
MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
472+
MT6358_BUCK("buck_vs1", VS1, "vsys-vs1", 1000000, 2587500, 12500,
471473
0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
472-
MT6358_REG_FIXED("ldo_vrf12", VRF12,
473-
MT6358_LDO_VRF12_CON0, 0, 1200000),
474-
MT6358_REG_FIXED("ldo_vio18", VIO18,
475-
MT6358_LDO_VIO18_CON0, 0, 1800000),
476-
MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
477-
MT6358_LDO_VCAMIO_CON0, 0, 1800000),
478-
MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
479-
MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
480-
MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
481-
MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
482-
MT6358_REG_FIXED("ldo_vaux18", VAUX18,
483-
MT6358_LDO_VAUX18_CON0, 0, 1800000),
484-
MT6358_REG_FIXED("ldo_vbif28", VBIF28,
485-
MT6358_LDO_VBIF28_CON0, 0, 2800000),
486-
MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
487-
MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
488-
MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
489-
MT6358_REG_FIXED("ldo_vaud28", VAUD28,
490-
MT6358_LDO_VAUD28_CON0, 0, 2800000),
491-
MT6358_LDO("ldo_vdram2", VDRAM2, vdram2,
474+
MT6358_REG_FIXED("ldo_vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
475+
MT6358_REG_FIXED("ldo_vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
476+
MT6358_REG_FIXED("ldo_vcamio", VCAMIO, "vs1-ldo1", MT6358_LDO_VCAMIO_CON0, 0, 1800000),
477+
MT6358_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo1", MT6358_LDO_VCN18_CON0, 0, 1800000),
478+
MT6358_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
479+
MT6358_REG_FIXED("ldo_vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
480+
MT6358_REG_FIXED("ldo_vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
481+
MT6358_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
482+
MT6358_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
483+
MT6358_REG_FIXED("ldo_vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
484+
MT6358_REG_FIXED("ldo_va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
485+
MT6358_REG_FIXED("ldo_vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
486+
MT6358_REG_FIXED("ldo_vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
487+
MT6358_LDO("ldo_vdram2", VDRAM2, "vs2-ldo1", vdram2,
492488
MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
493-
MT6358_LDO("ldo_vsim1", VSIM1, vsim,
489+
MT6358_LDO("ldo_vsim1", VSIM1, "vsys-ldo1", vsim,
494490
MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
495-
MT6358_LDO("ldo_vibr", VIBR, vibr,
491+
MT6358_LDO("ldo_vibr", VIBR, "vsys-ldo3", vibr,
496492
MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
497-
MT6358_LDO("ldo_vusb", VUSB, vusb,
493+
MT6358_LDO("ldo_vusb", VUSB, "vsys-ldo1", vusb,
498494
MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
499-
MT6358_LDO("ldo_vcamd", VCAMD, vcamd,
495+
MT6358_LDO("ldo_vcamd", VCAMD, "vs2-ldo4", vcamd,
500496
MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
501-
MT6358_LDO("ldo_vefuse", VEFUSE, vefuse,
497+
MT6358_LDO("ldo_vefuse", VEFUSE, "vs1-ldo1", vefuse,
502498
MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
503-
MT6358_LDO("ldo_vmch", VMCH, vmch_vemc,
499+
MT6358_LDO("ldo_vmch", VMCH, "vsys-ldo2", vmch_vemc,
504500
MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
505-
MT6358_LDO("ldo_vcama1", VCAMA1, vcama,
501+
MT6358_LDO("ldo_vcama1", VCAMA1, "vsys-ldo3", vcama,
506502
MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
507-
MT6358_LDO("ldo_vemc", VEMC, vmch_vemc,
503+
MT6358_LDO("ldo_vemc", VEMC, "vsys-ldo2", vmch_vemc,
508504
MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
509-
MT6358_LDO("ldo_vcn33", VCN33, vcn33,
505+
MT6358_LDO("ldo_vcn33", VCN33, "vsys-ldo3", vcn33,
510506
MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
511-
MT6358_LDO("ldo_vcama2", VCAMA2, vcama,
507+
MT6358_LDO("ldo_vcama2", VCAMA2, "vsys-ldo3", vcama,
512508
MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
513-
MT6358_LDO("ldo_vmc", VMC, vmc,
509+
MT6358_LDO("ldo_vmc", VMC, "vsys-ldo2", vmc,
514510
MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
515-
MT6358_LDO("ldo_vldo28", VLDO28, vldo28,
511+
MT6358_LDO("ldo_vldo28", VLDO28, "vsys-ldo2", vldo28,
516512
MT6358_LDO_VLDO28_CON0_0, 0,
517513
MT6358_VLDO28_ANA_CON0, 0x300),
518-
MT6358_LDO("ldo_vsim2", VSIM2, vsim,
514+
MT6358_LDO("ldo_vsim2", VSIM2, "vsys-ldo2", vsim,
519515
MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
520-
MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
516+
MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, "vs2-ldo3", 500000, 1293750, 6250,
521517
MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
522-
MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
518+
MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, "vs2-ldo3", 500000, 1293750, 6250,
523519
MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
524-
MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
520+
MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, "vs2-ldo3", 500000, 1293750, 6250,
525521
MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
526-
MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
522+
MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, "vs2-ldo3", 500000, 1293750, 6250,
527523
MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
528524
};
529525

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