Skip to content

Commit 3efe848

Browse files
marcanjannau
authored andcommitted
wifi: brcmfmac: Handle watchdog properly in newer cores
On newer cores, we need to explicitly set the subsystems to reset via the watchdog. Logic adapted from bcmdhd. Signed-off-by: Hector Martin <marcan@marcan.st>
1 parent 9a4ef65 commit 3efe848

2 files changed

Lines changed: 32 additions & 2 deletions

File tree

drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c

Lines changed: 24 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -739,8 +739,30 @@ static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
739739

740740
/* Watchdog reset */
741741
brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
742-
WRITECC32(devinfo, watchdog, 4);
743-
msleep(100);
742+
core = brcmf_chip_get_chipcommon(devinfo->ci);
743+
744+
if (core->rev >= 65) {
745+
u32 mask = CC_WD_SSRESET_PCIE_F0_EN;
746+
747+
core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
748+
if (core->rev < 66)
749+
mask |= CC_WD_SSRESET_PCIE_ALL_FN_EN;
750+
751+
val = READCC32(devinfo, watchdog);
752+
val &= ~CC_WD_ENABLE_MASK;
753+
val |= mask;
754+
WRITECC32(devinfo, watchdog, val);
755+
val &= ~CC_WD_COUNTER_MASK;
756+
val |= 4;
757+
WRITECC32(devinfo, watchdog, val);
758+
msleep(10);
759+
val = READCC32(devinfo, intstatus);
760+
val |= mask;
761+
WRITECC32(devinfo, intstatus, val);
762+
} else {
763+
WRITECC32(devinfo, watchdog, 4);
764+
msleep(100);
765+
}
744766

745767
/* Restore ASPM */
746768
brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);

drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,14 @@ struct chipcregs {
302302
#define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27)
303303

304304

305+
/* watchdog */
306+
#define CC_WD_SSRESET_PCIE_F0_EN 0x10000000
307+
#define CC_WD_SSRESET_PCIE_F1_EN 0x20000000
308+
#define CC_WD_SSRESET_PCIE_F2_EN 0x40000000
309+
#define CC_WD_SSRESET_PCIE_ALL_FN_EN 0x80000000
310+
#define CC_WD_COUNTER_MASK 0x0fffffff
311+
#define CC_WD_ENABLE_MASK 0xf0000000
312+
305313
/*
306314
* Maximum delay for the PMU state transition in us.
307315
* This is an upper bound intended for spinwaits etc.

0 commit comments

Comments
 (0)