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tools arch x86: Sync msr-index.h to pick AMD64_{PERF_CNTR_GLOBAL_STATUS_SET,SAVIC_CONTROL}, IA32_L3_QOS_{ABMC,EXT}_CFG
To pick up the changes in: cdfed93 ("KVM: x86/pmu: Move PMU_CAP_{FW_WRITES,LBR_FMT} into msr-index.h header") bc6397c ("x86/cpu/topology: Define AMD64_CPUID_EXT_FEAT MSR") 84ecefb ("x86/resctrl: Add data structures and definitions for ABMC assignment") faebbc5 ("x86/resctrl: Add support to enable/disable AMD ABMC feature") c4074ab ("x86/apic: Enable Secure AVIC in the control MSR") 869e36b ("x86/apic: Allow NMI to be injected from hypervisor for Secure AVIC") 30c2b98 ("x86/apic: Add new driver for Secure AVIC") 0c5caea ("perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag") 68e61f6 ("KVM: SVM: Emulate PERF_CNTR_GLOBAL_STATUS_SET for PerfMonV2") a3c4f33 ("x86/msr-index: Add AMD workload classification MSRs") 65f55a3 ("x86/CPU/AMD: Add CPUID faulting support") 17ec2f9 ("KVM: VMX: Allow guest to set DEBUGCTL.RTM_DEBUG if RTM is supported") Addressing this tools/perf build warning: Warning: Kernel ABI header differences: diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h That makes the beautification scripts to pick some new entries: $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after $ diff -u before after --- before 2025-10-30 09:34:49.283533597 -0300 +++ after 2025-10-30 09:35:00.971426811 -0300 @@ -272,6 +272,9 @@ [0xc0000300 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_STATUS", [0xc0000301 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_CTL", [0xc0000302 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_STATUS_CLR", + [0xc0000303 - x86_64_specific_MSRs_offset] = "AMD64_PERF_CNTR_GLOBAL_STATUS_SET", + [0xc00003fd - x86_64_specific_MSRs_offset] = "IA32_L3_QOS_ABMC_CFG", + [0xc00003ff - x86_64_specific_MSRs_offset] = "IA32_L3_QOS_EXT_CFG", [0xc0000400 - x86_64_specific_MSRs_offset] = "IA32_EVT_CFG_BASE", [0xc0000500 - x86_64_specific_MSRs_offset] = "AMD_WORKLOAD_CLASS_CONFIG", [0xc0000501 - x86_64_specific_MSRs_offset] = "AMD_WORKLOAD_CLASS_ID", @@ -319,6 +322,7 @@ [0xc0010133 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_RMP_END", [0xc0010134 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_GUEST_TSC_FREQ", [0xc0010136 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_RMP_CFG", + [0xc0010138 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_SAVIC_CONTROL", [0xc0010140 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_OSVW_ID_LENGTH", [0xc0010141 - x86_AMD_V_KVM_MSRs_offset] = "AMD64_OSVW_STATUS", [0xc0010200 - x86_AMD_V_KVM_MSRs_offset] = "F15H_PERF_CTL", $ Now one can trace systemwide asking to see backtraces to where that MSR is being read/written: root@x1:~# perf trace -e msr:*_msr/max-stack=32/ --filter="msr==IA32_L3_QOS_ABMC_CFG" ^Croot@x1:~# If we use -v (verbose mode) we can see what it does behind the scenes: root@x1:~# perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==IA32_L3_QOS_ABMC_CFG" 0xc00003fd New filter for msr:write_msr: (msr==0xc00003fd) && (common_pid != 449842 && common_pid != 433756) 0xc00003fd New filter for msr:read_msr: (msr==0xc00003fd) && (common_pid != 449842 && common_pid != 433756) mmap size 528384B ^Croot@x1:~# Example with a frequent msr: # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==IA32_SPEC_CTRL" --max-events 2 Using CPUID AuthenticAMD-25-21-0 0x48 New filter for msr:read_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841) 0x48 New filter for msr:write_msr: (msr==0x48) && (common_pid != 2612129 && common_pid != 3841) mmap size 528384B Looking at the vmlinux_path (8 entries long) symsrc__init: build id mismatch for vmlinux. Using /proc/kcore for kernel data Using /proc/kallsyms for symbols 0.000 Timer/2525383 msr:write_msr(msr: IA32_SPEC_CTRL, val: 6) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __schedule ([kernel.kallsyms]) schedule ([kernel.kallsyms]) futex_wait_queue_me ([kernel.kallsyms]) futex_wait ([kernel.kallsyms]) do_futex ([kernel.kallsyms]) __x64_sys_futex ([kernel.kallsyms]) do_syscall_64 ([kernel.kallsyms]) entry_SYSCALL_64_after_hwframe ([kernel.kallsyms]) __futex_abstimed_wait_common64 (/usr/lib64/libpthread-2.33.so) 0.030 :0/0 msr:write_msr(msr: IA32_SPEC_CTRL, val: 2) do_trace_write_msr ([kernel.kallsyms]) do_trace_write_msr ([kernel.kallsyms]) __switch_to_xtra ([kernel.kallsyms]) __switch_to ([kernel.kallsyms]) __schedule ([kernel.kallsyms]) schedule_idle ([kernel.kallsyms]) do_idle ([kernel.kallsyms]) cpu_startup_entry ([kernel.kallsyms]) secondary_startup_64_no_verify ([kernel.kallsyms]) # Please see tools/include/uapi/README for further details. Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Babu Moger <babu.moger@amd.com> Cc: Dapeng Mi <dapeng1.mi@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: James Clark <james.clark@linaro.org> Cc: Jiri Olsa <jolsa@kernel.org> Cc: K Prateek Nayak <kprateek.nayak@amd.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com> Cc: Perry Yuan <perry.yuan@amd.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sean Christopherson <seanjc@google.com> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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‎tools/arch/x86/include/asm/msr-index.h‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -315,9 +315,12 @@
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#define PERF_CAP_PT_IDX 16
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#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
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#define PERF_CAP_LBR_FMT 0x3f
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#define PERF_CAP_PEBS_TRAP BIT_ULL(6)
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#define PERF_CAP_ARCH_REG BIT_ULL(7)
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#define PERF_CAP_PEBS_FORMAT 0xf00
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#define PERF_CAP_FW_WRITES BIT_ULL(13)
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#define PERF_CAP_PEBS_BASELINE BIT_ULL(14)
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#define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17)
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#define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \
@@ -633,6 +636,11 @@
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#define MSR_AMD_PPIN 0xc00102f1
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#define MSR_AMD64_CPUID_FN_7 0xc0011002
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#define MSR_AMD64_CPUID_FN_1 0xc0011004
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#define MSR_AMD64_CPUID_EXT_FEAT 0xc0011005
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#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT 54
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#define MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT BIT_ULL(MSR_AMD64_CPUID_EXT_FEAT_TOPOEXT_BIT)
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#define MSR_AMD64_LS_CFG 0xc0011020
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_TW_CFG 0xc0011023
@@ -701,8 +709,15 @@
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#define MSR_AMD64_SNP_VMSA_REG_PROT BIT_ULL(MSR_AMD64_SNP_VMSA_REG_PROT_BIT)
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#define MSR_AMD64_SNP_SMT_PROT_BIT 17
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#define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)
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#define MSR_AMD64_SNP_RESV_BIT 18
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#define MSR_AMD64_SNP_SECURE_AVIC_BIT 18
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#define MSR_AMD64_SNP_SECURE_AVIC BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)
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#define MSR_AMD64_SNP_RESV_BIT 19
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#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)
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#define MSR_AMD64_SAVIC_CONTROL 0xc0010138
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#define MSR_AMD64_SAVIC_EN_BIT 0
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#define MSR_AMD64_SAVIC_EN BIT_ULL(MSR_AMD64_SAVIC_EN_BIT)
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#define MSR_AMD64_SAVIC_ALLOWEDNMI_BIT 1
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#define MSR_AMD64_SAVIC_ALLOWEDNMI BIT_ULL(MSR_AMD64_SAVIC_ALLOWEDNMI_BIT)
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#define MSR_AMD64_RMP_BASE 0xc0010132
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#define MSR_AMD64_RMP_END 0xc0010133
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#define MSR_AMD64_RMP_CFG 0xc0010136
@@ -735,6 +750,7 @@
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300
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#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302
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#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET 0xc0000303
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/* AMD Hardware Feedback Support MSRs */
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#define MSR_AMD_WORKLOAD_CLASS_CONFIG 0xc0000500
@@ -1225,6 +1241,8 @@
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/* - AMD: */
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#define MSR_IA32_MBA_BW_BASE 0xc0000200
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#define MSR_IA32_SMBA_BW_BASE 0xc0000280
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#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd
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#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
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#define MSR_IA32_EVT_CFG_BASE 0xc0000400
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/* AMD-V MSRs */

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