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46 | 46 | #define LP55xx_MODE_ENGn_GET(n, mode, shift) \ |
47 | 47 | (((mode) >> LP55xx_MODE_ENGn_SHIFT(n, shift)) & LP55xx_MODE_ENG_MASK) |
48 | 48 |
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| 49 | +#define LP55xx_EXEC_ENG_MASK GENMASK(1, 0) |
| 50 | +#define LP55xx_EXEC_HOLD_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x0) |
| 51 | +#define LP55xx_EXEC_STEP_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x1) |
| 52 | +#define LP55xx_EXEC_RUN_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x2) |
| 53 | +#define LP55xx_EXEC_ONCE_ENG FIELD_PREP_CONST(LP55xx_EXEC_ENG_MASK, 0x3) |
| 54 | + |
| 55 | +#define LP55xx_EXEC_ENGn_SHIFT(n, shift) ((shift) + (2 * (3 - (n)))) |
| 56 | +#define LP55xx_EXEC_ENGn_MASK(n, shift) (LP55xx_EXEC_ENG_MASK << LP55xx_EXEC_ENGn_SHIFT(n, shift)) |
| 57 | + |
49 | 58 | /* Memory Page Selection */ |
50 | 59 | #define LP55xx_REG_PROG_PAGE_SEL 0x4f |
51 | 60 | /* If supported, each ENGINE have an equal amount of pages offset from page 0 */ |
@@ -117,6 +126,40 @@ void lp55xx_load_engine(struct lp55xx_chip *chip) |
117 | 126 | } |
118 | 127 | EXPORT_SYMBOL_GPL(lp55xx_load_engine); |
119 | 128 |
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| 129 | +int lp55xx_run_engine_common(struct lp55xx_chip *chip) |
| 130 | +{ |
| 131 | + const struct lp55xx_device_config *cfg = chip->cfg; |
| 132 | + u8 mode, exec; |
| 133 | + int i, ret; |
| 134 | + |
| 135 | + /* To run the engine, both OP MODE and EXEC needs to be put in RUN mode */ |
| 136 | + ret = lp55xx_read(chip, cfg->reg_op_mode.addr, &mode); |
| 137 | + if (ret) |
| 138 | + return ret; |
| 139 | + |
| 140 | + ret = lp55xx_read(chip, cfg->reg_exec.addr, &exec); |
| 141 | + if (ret) |
| 142 | + return ret; |
| 143 | + |
| 144 | + /* Switch to RUN only for engine that were put in LOAD previously */ |
| 145 | + for (i = LP55XX_ENGINE_1; i <= LP55XX_ENGINE_3; i++) { |
| 146 | + if (LP55xx_MODE_ENGn_GET(i, mode, cfg->reg_op_mode.shift) != LP55xx_MODE_LOAD_ENG) |
| 147 | + continue; |
| 148 | + |
| 149 | + mode &= ~LP55xx_MODE_ENGn_MASK(i, cfg->reg_op_mode.shift); |
| 150 | + mode |= LP55xx_MODE_RUN_ENG << LP55xx_MODE_ENGn_SHIFT(i, cfg->reg_op_mode.shift); |
| 151 | + exec &= ~LP55xx_EXEC_ENGn_MASK(i, cfg->reg_exec.shift); |
| 152 | + exec |= LP55xx_EXEC_RUN_ENG << LP55xx_EXEC_ENGn_SHIFT(i, cfg->reg_exec.shift); |
| 153 | + } |
| 154 | + |
| 155 | + lp55xx_write(chip, cfg->reg_op_mode.addr, mode); |
| 156 | + lp55xx_wait_opmode_done(chip); |
| 157 | + lp55xx_write(chip, cfg->reg_exec.addr, exec); |
| 158 | + |
| 159 | + return 0; |
| 160 | +} |
| 161 | +EXPORT_SYMBOL_GPL(lp55xx_run_engine_common); |
| 162 | + |
120 | 163 | static void lp55xx_reset_device(struct lp55xx_chip *chip) |
121 | 164 | { |
122 | 165 | const struct lp55xx_device_config *cfg = chip->cfg; |
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