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airliedairlied
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Merge tag 'drm-misc-fixes-2025-09-03' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes
Two nouveau interrupt handling fixes, one race fix for ivpu, a race fix for drm_sched, and a clock fix for ti-sn65dsi86. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@redhat.com> Link: https://lore.kernel.org/r/qc2rd7bskgufjtyspbjflyjpswcnhyja6s7nm2yb67j7hezyey@yfn2w6n5trff
2 parents b320789 + bdd5a14 commit 42e0a73

13 files changed

Lines changed: 135 additions & 18 deletions

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‎MAINTAINERS‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7820,7 +7820,7 @@ Q: https://patchwork.freedesktop.org/project/nouveau/
78207820
Q: https://gitlab.freedesktop.org/drm/nouveau/-/merge_requests
78217821
B: https://gitlab.freedesktop.org/drm/nouveau/-/issues
78227822
C: irc://irc.oftc.net/nouveau
7823-
T: git https://gitlab.freedesktop.org/drm/nouveau.git
7823+
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
78247824
F: drivers/gpu/drm/nouveau/
78257825
F: include/uapi/drm/nouveau_drm.h
78267826

‎drivers/accel/ivpu/ivpu_drv.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ static void ivpu_bo_unbind_all_user_contexts(struct ivpu_device *vdev)
677677
static void ivpu_dev_fini(struct ivpu_device *vdev)
678678
{
679679
ivpu_jobs_abort_all(vdev);
680-
ivpu_pm_cancel_recovery(vdev);
680+
ivpu_pm_disable_recovery(vdev);
681681
ivpu_pm_disable(vdev);
682682
ivpu_prepare_for_reset(vdev);
683683
ivpu_shutdown(vdev);

‎drivers/accel/ivpu/ivpu_pm.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -417,10 +417,10 @@ void ivpu_pm_init(struct ivpu_device *vdev)
417417
ivpu_dbg(vdev, PM, "Autosuspend delay = %d\n", delay);
418418
}
419419

420-
void ivpu_pm_cancel_recovery(struct ivpu_device *vdev)
420+
void ivpu_pm_disable_recovery(struct ivpu_device *vdev)
421421
{
422422
drm_WARN_ON(&vdev->drm, delayed_work_pending(&vdev->pm->job_timeout_work));
423-
cancel_work_sync(&vdev->pm->recovery_work);
423+
disable_work_sync(&vdev->pm->recovery_work);
424424
}
425425

426426
void ivpu_pm_enable(struct ivpu_device *vdev)

‎drivers/accel/ivpu/ivpu_pm.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ struct ivpu_pm_info {
2525
void ivpu_pm_init(struct ivpu_device *vdev);
2626
void ivpu_pm_enable(struct ivpu_device *vdev);
2727
void ivpu_pm_disable(struct ivpu_device *vdev);
28-
void ivpu_pm_cancel_recovery(struct ivpu_device *vdev);
28+
void ivpu_pm_disable_recovery(struct ivpu_device *vdev);
2929

3030
int ivpu_pm_suspend_cb(struct device *dev);
3131
int ivpu_pm_resume_cb(struct device *dev);

‎drivers/gpu/drm/bridge/ti-sn65dsi86.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -392,6 +392,17 @@ static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
392392

393393
gpiod_set_value_cansleep(pdata->enable_gpio, 1);
394394

395+
/*
396+
* After EN is deasserted and an external clock is detected, the bridge
397+
* will sample GPIO3:1 to determine its frequency. The driver will
398+
* overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is
399+
* racy. Thus we have to wait a couple of us. According to the datasheet
400+
* the GPIO lines has to be stable at least 5 us (td5) but it seems that
401+
* is not enough and the refclk frequency value is still lost or
402+
* overwritten by the bridge itself. Waiting for 20us seems to work.
403+
*/
404+
usleep_range(20, 30);
405+
395406
/*
396407
* If we have a reference clock we can enable communication w/ the
397408
* panel (including the aux channel) w/out any need for an input clock

‎drivers/gpu/drm/nouveau/gv100_fence.c‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
1818
struct nvif_push *push = &chan->chan.push;
1919
int ret;
2020

21-
ret = PUSH_WAIT(push, 8);
21+
ret = PUSH_WAIT(push, 13);
2222
if (ret)
2323
return ret;
2424

@@ -32,6 +32,11 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
3232
NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) |
3333
NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS));
3434

35+
PUSH_MTHD(push, NVC36F, MEM_OP_A, 0,
36+
MEM_OP_B, 0,
37+
MEM_OP_C, NVDEF(NVC36F, MEM_OP_C, MEMBAR_TYPE, SYS_MEMBAR),
38+
MEM_OP_D, NVDEF(NVC36F, MEM_OP_D, OPERATION, MEMBAR));
39+
3540
PUSH_MTHD(push, NVC36F, NON_STALL_INTERRUPT, 0);
3641

3742
PUSH_KICK(push);

‎drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h‎

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,91 @@
77

88
#define NVC36F_NON_STALL_INTERRUPT (0x00000020)
99
#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0
10+
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
11+
// specifying the page address for a targeted TLB invalidate and the uTLB for
12+
// a targeted REPLAY_CANCEL for UVM.
13+
// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
14+
// rearranged fields.
15+
#define NVC36F_MEM_OP_A (0x00000028)
16+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
17+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
18+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
19+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
20+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
21+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
22+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
23+
#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
24+
#define NVC36F_MEM_OP_B (0x0000002c)
25+
#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
26+
#define NVC36F_MEM_OP_C (0x00000030)
27+
#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0
28+
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
29+
#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
30+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
31+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
32+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
33+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
34+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
35+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
36+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
37+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
38+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
39+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
40+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
41+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
42+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
43+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
44+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
45+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
46+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
47+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
48+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
49+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
50+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
51+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
52+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
53+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
54+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
55+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
56+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
57+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
58+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
59+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
60+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
61+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
62+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
63+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
64+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
65+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
66+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
67+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
68+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
69+
#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
70+
#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
71+
// MEM_OP_D MUST be preceded by MEM_OPs A-C.
72+
#define NVC36F_MEM_OP_D (0x00000034)
73+
#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
74+
#define NVC36F_MEM_OP_D_OPERATION 31:27
75+
#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
76+
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
77+
#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
78+
#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
79+
#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
80+
// CLEAN_LINES is an alias for Tegra/GPU IP usage
81+
#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
82+
#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
83+
#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
84+
#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
85+
#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
86+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
87+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
88+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
89+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
90+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
91+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
92+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
93+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
94+
#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
1095
#define NVC36F_SEM_ADDR_LO (0x0000005c)
1196
#define NVC36F_SEM_ADDR_LO_OFFSET 31:2
1297
#define NVC36F_SEM_ADDR_HI (0x00000060)

‎drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)
350350
nvkm_chid_unref(&fifo->chid);
351351

352352
nvkm_event_fini(&fifo->nonstall.event);
353+
if (fifo->func->nonstall_dtor)
354+
fifo->func->nonstall_dtor(fifo);
353355
mutex_destroy(&fifo->mutex);
354356

355357
if (fifo->func->dtor)

‎drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c‎

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)
517517
static void
518518
ga100_fifo_nonstall_block(struct nvkm_event *event, int type, int index)
519519
{
520-
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
521-
struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
522-
523-
nvkm_inth_block(&runl->nonstall.inth);
524520
}
525521

526522
static void
527523
ga100_fifo_nonstall_allow(struct nvkm_event *event, int type, int index)
528524
{
529-
struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), nonstall.event);
530-
struct nvkm_runl *runl = nvkm_runl_get(fifo, index, 0);
531-
532-
nvkm_inth_allow(&runl->nonstall.inth);
533525
}
534526

535527
const struct nvkm_event_func
@@ -564,12 +556,26 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)
564556
if (ret)
565557
return ret;
566558

559+
nvkm_inth_allow(&runl->nonstall.inth);
560+
567561
nr = max(nr, runl->id + 1);
568562
}
569563

570564
return nr;
571565
}
572566

567+
void
568+
ga100_fifo_nonstall_dtor(struct nvkm_fifo *fifo)
569+
{
570+
struct nvkm_runl *runl;
571+
572+
nvkm_runl_foreach(runl, fifo) {
573+
if (runl->nonstall.vector < 0)
574+
continue;
575+
nvkm_inth_block(&runl->nonstall.inth);
576+
}
577+
}
578+
573579
int
574580
ga100_fifo_runl_ctor(struct nvkm_fifo *fifo)
575581
{
@@ -599,6 +605,7 @@ ga100_fifo = {
599605
.runl_ctor = ga100_fifo_runl_ctor,
600606
.mmu_fault = &tu102_fifo_mmu_fault,
601607
.nonstall_ctor = ga100_fifo_nonstall_ctor,
608+
.nonstall_dtor = ga100_fifo_nonstall_dtor,
602609
.nonstall = &ga100_fifo_nonstall,
603610
.runl = &ga100_runl,
604611
.runq = &ga100_runq,

‎drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ ga102_fifo = {
3030
.runl_ctor = ga100_fifo_runl_ctor,
3131
.mmu_fault = &tu102_fifo_mmu_fault,
3232
.nonstall_ctor = ga100_fifo_nonstall_ctor,
33+
.nonstall_dtor = ga100_fifo_nonstall_dtor,
3334
.nonstall = &ga100_fifo_nonstall,
3435
.runl = &ga100_runl,
3536
.runq = &ga100_runq,

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