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Sota4Everkrzk
Sota4Ever
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krzk
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dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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‎Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml‎

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properties:
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compatible:
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enum:
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- samsung,exynos990-cmu-peric1
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- samsung,exynos990-cmu-peric0
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- samsung,exynos990-cmu-hsi0
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- samsung,exynos990-cmu-peris
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- samsung,exynos990-cmu-top
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- reg
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos990-cmu-peric1
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- samsung,exynos990-cmu-peric0
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then:
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properties:
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clocks:
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items:
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- description: External reference clock (26 MHz)
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- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
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- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
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clock-names:
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items:
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- const: oscclk
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- const: bus
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- const: ip
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- if:
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properties:
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compatible:

‎include/dt-bindings/clock/samsung,exynos990.h‎

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#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
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#define CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_CLK 23
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/* CMU_PERIC0 */
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#define CLK_MOUT_PERIC0_BUS_USER 1
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#define CLK_MOUT_PERIC0_UART_DBG 2
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#define CLK_MOUT_PERIC0_USI00_USI_USER 3
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#define CLK_MOUT_PERIC0_USI01_USI_USER 4
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#define CLK_MOUT_PERIC0_USI02_USI_USER 5
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#define CLK_MOUT_PERIC0_USI03_USI_USER 6
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#define CLK_MOUT_PERIC0_USI04_USI_USER 7
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#define CLK_MOUT_PERIC0_USI05_USI_USER 8
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#define CLK_MOUT_PERIC0_USI13_USI_USER 9
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#define CLK_MOUT_PERIC0_USI14_USI_USER 10
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#define CLK_MOUT_PERIC0_USI15_USI_USER 11
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#define CLK_MOUT_PERIC0_USI_I2C_USER 12
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#define CLK_DOUT_PERIC0_UART_DBG 13
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#define CLK_DOUT_PERIC0_USI00_USI 14
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#define CLK_DOUT_PERIC0_USI01_USI 15
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#define CLK_DOUT_PERIC0_USI02_USI 16
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#define CLK_DOUT_PERIC0_USI03_USI 17
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#define CLK_DOUT_PERIC0_USI04_USI 18
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#define CLK_DOUT_PERIC0_USI05_USI 19
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#define CLK_DOUT_PERIC0_USI13_USI 20
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#define CLK_DOUT_PERIC0_USI14_USI 21
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#define CLK_DOUT_PERIC0_USI15_USI 22
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#define CLK_DOUT_PERIC0_USI_I2C 23
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#define CLK_GOUT_PERIC0_CMU_PCLK 24
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#define CLK_GOUT_PERIC0_OSCCLK_CLK 25
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#define CLK_GOUT_PERIC0_D_TZPC_PCLK 26
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#define CLK_GOUT_PERIC0_GPIO_PCLK 27
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#define CLK_GOUT_PERIC0_LHM_AXI_P_CLK 28
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_10 29
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_11 30
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_12 31
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_13 32
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_14 33
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_15 34
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_4 35
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_5 36
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_6 37
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_7 38
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_8 39
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#define CLK_GOUT_PERIC0_TOP0_IPCLK_9 40
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#define CLK_GOUT_PERIC0_TOP0_PCLK_10 41
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#define CLK_GOUT_PERIC0_TOP0_PCLK_11 42
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#define CLK_GOUT_PERIC0_TOP0_PCLK_12 43
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#define CLK_GOUT_PERIC0_TOP0_PCLK_13 44
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#define CLK_GOUT_PERIC0_TOP0_PCLK_14 45
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#define CLK_GOUT_PERIC0_TOP0_PCLK_15 46
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#define CLK_GOUT_PERIC0_TOP0_PCLK_4 47
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#define CLK_GOUT_PERIC0_TOP0_PCLK_5 48
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#define CLK_GOUT_PERIC0_TOP0_PCLK_6 49
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#define CLK_GOUT_PERIC0_TOP0_PCLK_7 50
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#define CLK_GOUT_PERIC0_TOP0_PCLK_8 51
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#define CLK_GOUT_PERIC0_TOP0_PCLK_9 52
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_0 53
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_3 54
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_4 55
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_5 56
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_6 57
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_7 58
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#define CLK_GOUT_PERIC0_TOP1_IPCLK_8 59
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#define CLK_GOUT_PERIC0_TOP1_PCLK_0 60
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#define CLK_GOUT_PERIC0_TOP1_PCLK_15 61
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#define CLK_GOUT_PERIC0_TOP1_PCLK_3 62
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#define CLK_GOUT_PERIC0_TOP1_PCLK_4 63
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#define CLK_GOUT_PERIC0_TOP1_PCLK_5 64
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#define CLK_GOUT_PERIC0_TOP1_PCLK_6 65
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#define CLK_GOUT_PERIC0_TOP1_PCLK_7 66
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#define CLK_GOUT_PERIC0_TOP1_PCLK_8 67
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#define CLK_GOUT_PERIC0_BUSP_CLK 68
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#define CLK_GOUT_PERIC0_UART_DBG_CLK 69
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#define CLK_GOUT_PERIC0_USI00_USI_CLK 70
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#define CLK_GOUT_PERIC0_USI01_USI_CLK 71
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#define CLK_GOUT_PERIC0_USI02_USI_CLK 72
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#define CLK_GOUT_PERIC0_USI03_USI_CLK 73
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#define CLK_GOUT_PERIC0_USI04_USI_CLK 74
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#define CLK_GOUT_PERIC0_USI05_USI_CLK 75
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#define CLK_GOUT_PERIC0_USI13_USI_CLK 76
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#define CLK_GOUT_PERIC0_USI14_USI_CLK 77
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#define CLK_GOUT_PERIC0_USI15_USI_CLK 78
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#define CLK_GOUT_PERIC0_USI_I2C_CLK 79
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#define CLK_GOUT_PERIC0_SYSREG_PCLK 80
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/* CMU_PERIC1 */
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#define CLK_MOUT_PERIC1_BUS_USER 1
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#define CLK_MOUT_PERIC1_UART_BT_USER 2
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#define CLK_MOUT_PERIC1_USI06_USI_USER 3
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#define CLK_MOUT_PERIC1_USI07_USI_USER 4
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#define CLK_MOUT_PERIC1_USI08_USI_USER 5
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#define CLK_MOUT_PERIC1_USI09_USI_USER 6
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#define CLK_MOUT_PERIC1_USI10_USI_USER 7
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#define CLK_MOUT_PERIC1_USI11_USI_USER 8
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#define CLK_MOUT_PERIC1_USI12_USI_USER 9
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#define CLK_MOUT_PERIC1_USI18_USI_USER 10
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#define CLK_MOUT_PERIC1_USI16_USI_USER 11
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#define CLK_MOUT_PERIC1_USI17_USI_USER 12
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#define CLK_MOUT_PERIC1_USI_I2C_USER 13
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#define CLK_DOUT_PERIC1_UART_BT 14
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#define CLK_DOUT_PERIC1_USI06_USI 15
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#define CLK_DOUT_PERIC1_USI07_USI 16
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#define CLK_DOUT_PERIC1_USI08_USI 17
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#define CLK_DOUT_PERIC1_USI18_USI 18
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#define CLK_DOUT_PERIC1_USI12_USI 19
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#define CLK_DOUT_PERIC1_USI09_USI 20
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#define CLK_DOUT_PERIC1_USI10_USI 21
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#define CLK_DOUT_PERIC1_USI11_USI 22
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#define CLK_DOUT_PERIC1_USI16_USI 23
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#define CLK_DOUT_PERIC1_USI17_USI 24
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#define CLK_DOUT_PERIC1_USI_I2C 25
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#define CLK_GOUT_PERIC1_CMU_PCLK 26
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#define CLK_GOUT_PERIC1_UART_BT_CLK 27
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#define CLK_GOUT_PERIC1_USI12_USI_CLK 28
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#define CLK_GOUT_PERIC1_USI18_USI_CLK 29
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#define CLK_GOUT_PERIC1_D_TZPC_PCLK 30
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#define CLK_GOUT_PERIC1_GPIO_PCLK 31
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#define CLK_GOUT_PERIC1_LHM_AXI_P_CSIS_CLK 32
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#define CLK_GOUT_PERIC1_LHM_AXI_P_CLK 33
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_10 34
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_11 35
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_12 36
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_13 37
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_14 38
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_15 39
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#define CLK_GOUT_PERIC1_TOP0_IPCLK_4 40
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#define CLK_GOUT_PERIC1_TOP0_PCLK_10 41
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#define CLK_GOUT_PERIC1_TOP0_PCLK_11 42
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#define CLK_GOUT_PERIC1_TOP0_PCLK_12 43
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#define CLK_GOUT_PERIC1_TOP0_PCLK_13 44
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#define CLK_GOUT_PERIC1_TOP0_PCLK_14 45
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#define CLK_GOUT_PERIC1_TOP0_PCLK_15 46
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#define CLK_GOUT_PERIC1_TOP0_PCLK_4 47
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_0 48
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_1 49
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_10 50
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_12 51
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_13 52
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_14 53
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_15 54
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_2 55
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_3 56
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_4 57
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_5 58
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_6 59
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_7 60
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#define CLK_GOUT_PERIC1_TOP1_IPCLK_9 61
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#define CLK_GOUT_PERIC1_TOP1_PCLK_0 62
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#define CLK_GOUT_PERIC1_TOP1_PCLK_1 63
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#define CLK_GOUT_PERIC1_TOP1_PCLK_10 64
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#define CLK_GOUT_PERIC1_TOP1_PCLK_12 65
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#define CLK_GOUT_PERIC1_TOP1_PCLK_13 66
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#define CLK_GOUT_PERIC1_TOP1_PCLK_14 67
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#define CLK_GOUT_PERIC1_TOP1_PCLK_15 68
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#define CLK_GOUT_PERIC1_TOP1_PCLK_2 69
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#define CLK_GOUT_PERIC1_TOP1_PCLK_3 70
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#define CLK_GOUT_PERIC1_TOP1_PCLK_4 71
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#define CLK_GOUT_PERIC1_TOP1_PCLK_5 72
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#define CLK_GOUT_PERIC1_TOP1_PCLK_6 73
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#define CLK_GOUT_PERIC1_TOP1_PCLK_7 74
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#define CLK_GOUT_PERIC1_TOP1_PCLK_9 75
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#define CLK_GOUT_PERIC1_BUSP_CLK 76
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#define CLK_GOUT_PERIC1_OSCCLK_CLK 77
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#define CLK_GOUT_PERIC1_USI06_USI_CLK 78
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#define CLK_GOUT_PERIC1_USI07_USI_CLK 79
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#define CLK_GOUT_PERIC1_USI08_USI_CLK 80
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#define CLK_GOUT_PERIC1_USI09_USI_CLK 81
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#define CLK_GOUT_PERIC1_USI10_USI_CLK 82
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#define CLK_GOUT_PERIC1_USI11_USI_CLK 83
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#define CLK_GOUT_PERIC1_USI16_USI_CLK 84
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#define CLK_GOUT_PERIC1_USI17_USI_CLK 85
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#define CLK_GOUT_PERIC1_USI_I2C_CLK 86
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#define CLK_GOUT_PERIC1_SYSREG_PCLK 87
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#define CLK_GOUT_PERIC1_USI16_I3C_PCLK 88
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#define CLK_GOUT_PERIC1_USI16_I3C_SCLK 89
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#define CLK_GOUT_PERIC1_USI17_I3C_PCLK 90
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#define CLK_GOUT_PERIC1_USI17_I3C_SCLK 91
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#define CLK_GOUT_PERIC1_XIU_P_ACLK 92
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/* CMU_PERIS */
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#define CLK_MOUT_PERIS_BUS_USER 1
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#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2

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