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vsyrjalavsyrjala
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drm/i915/de: Use intel_de_wait_us()
Convert some of the intel_de_wait_custom() users over to intel_de_wait_us(). We'll eventually want to eliminate intel_de_wait_custom() as it's a hinderance towards using poll_timeout_us(). This includes all the obvious cases where we only specify a microsecond timeout to intel_de_wait_custom(). Done with cocci (with manual formatting fixes): @@ expression display, reg, mask, value, timeout_us, out_value; @@ - intel_de_wait_custom(display, reg, mask, value, timeout_us, 0, out_value) + intel_de_wait_us(display, reg, mask, value, timeout_us, out_value) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-6-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
1 parent c6494d1 commit 45554c1

8 files changed

Lines changed: 67 additions & 83 deletions

File tree

‎drivers/gpu/drm/i915/display/icl_dsi.c‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -148,9 +148,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
148148
for_each_dsi_port(port, intel_dsi->ports) {
149149
dsi_trans = dsi_port_to_transcoder(port);
150150

151-
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
152-
LPTX_IN_PROGRESS, 0,
153-
20, 0, NULL);
151+
ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
152+
LPTX_IN_PROGRESS, 0, 20, NULL);
154153
if (ret)
155154
drm_err(display->drm, "LPTX bit not cleared\n");
156155
}
@@ -534,9 +533,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
534533
for_each_dsi_port(port, intel_dsi->ports) {
535534
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
536535

537-
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
538-
DDI_BUF_IS_IDLE, 0,
539-
500, 0, NULL);
536+
ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
537+
DDI_BUF_IS_IDLE, 0, 500, NULL);
540538
if (ret)
541539
drm_err(display->drm, "DDI port:%c buffer idle\n",
542540
port_name(port));
@@ -857,9 +855,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
857855

858856
dsi_trans = dsi_port_to_transcoder(port);
859857

860-
ret = intel_de_wait_custom(display, DSI_TRANS_FUNC_CONF(dsi_trans),
861-
LINK_READY, LINK_READY,
862-
2500, 0, NULL);
858+
ret = intel_de_wait_us(display,
859+
DSI_TRANS_FUNC_CONF(dsi_trans),
860+
LINK_READY, LINK_READY, 2500, NULL);
863861
if (ret)
864862
drm_err(display->drm, "DSI link not ready\n");
865863
}
@@ -1358,9 +1356,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
13581356
tmp &= ~LINK_ULPS_TYPE_LP11;
13591357
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
13601358

1361-
ret = intel_de_wait_custom(display, DSI_LP_MSG(dsi_trans),
1362-
LINK_IN_ULPS, LINK_IN_ULPS,
1363-
10, 0, NULL);
1359+
ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
1360+
LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
13641361
if (ret)
13651362
drm_err(display->drm, "DSI link not in ULPS\n");
13661363
}
@@ -1395,9 +1392,9 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
13951392
for_each_dsi_port(port, intel_dsi->ports) {
13961393
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
13971394

1398-
ret = intel_de_wait_custom(display, DDI_BUF_CTL(port),
1399-
DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE,
1400-
8, 0, NULL);
1395+
ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
1396+
DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
1397+
NULL);
14011398

14021399
if (ret)
14031400
drm_err(display->drm,

‎drivers/gpu/drm/i915/display/intel_cdclk.c‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -902,9 +902,8 @@ static void bdw_set_cdclk(struct intel_display *display,
902902
* According to the spec, it should be enough to poll for this 1 us.
903903
* However, extensive testing shows that this can take longer.
904904
*/
905-
ret = intel_de_wait_custom(display, LCPLL_CTL,
906-
LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
907-
100, 0, NULL);
905+
ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
906+
LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
908907
if (ret)
909908
drm_err(display->drm, "Switching to FCLK failed\n");
910909

@@ -914,9 +913,8 @@ static void bdw_set_cdclk(struct intel_display *display,
914913
intel_de_rmw(display, LCPLL_CTL,
915914
LCPLL_CD_SOURCE_FCLK, 0);
916915

917-
ret = intel_de_wait_custom(display, LCPLL_CTL,
918-
LCPLL_CD_SOURCE_FCLK_DONE, 0,
919-
1, 0, NULL);
916+
ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
917+
0, 1, NULL);
920918
if (ret)
921919
drm_err(display->drm, "Switching back to LCPLL failed\n");
922920

‎drivers/gpu/drm/i915/display/intel_cx0_phy.c‎

Lines changed: 23 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2888,20 +2888,20 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
28882888
XELPDP_LANE_PHY_CURRENT_STATUS(1))
28892889
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
28902890

2891-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
2892-
XELPDP_PORT_BUF_SOC_PHY_READY,
2893-
XELPDP_PORT_BUF_SOC_PHY_READY,
2894-
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
2891+
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
2892+
XELPDP_PORT_BUF_SOC_PHY_READY,
2893+
XELPDP_PORT_BUF_SOC_PHY_READY,
2894+
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, NULL))
28952895
drm_warn(display->drm,
28962896
"PHY %c failed to bring out of SOC reset\n",
28972897
phy_name(phy));
28982898

28992899
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
29002900
lane_pipe_reset);
29012901

2902-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
2903-
lane_phy_current_status, lane_phy_current_status,
2904-
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
2902+
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2903+
lane_phy_current_status, lane_phy_current_status,
2904+
XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
29052905
drm_warn(display->drm,
29062906
"PHY %c failed to bring out of lane reset\n",
29072907
phy_name(phy));
@@ -2910,10 +2910,10 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
29102910
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
29112911
intel_cx0_get_pclk_refclk_request(lane_mask));
29122912

2913-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
2914-
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
2915-
intel_cx0_get_pclk_refclk_ack(lane_mask),
2916-
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
2913+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
2914+
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
2915+
intel_cx0_get_pclk_refclk_ack(lane_mask),
2916+
XELPDP_REFCLK_ENABLE_TIMEOUT_US, NULL))
29172917
drm_warn(display->drm,
29182918
"PHY %c failed to request refclk\n",
29192919
phy_name(phy));
@@ -3064,10 +3064,10 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
30643064
intel_cx0_get_pclk_pll_request(maxpclk_lane));
30653065

30663066
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
3067-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3068-
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
3069-
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
3070-
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
3067+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3068+
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
3069+
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
3070+
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, NULL))
30713071
drm_warn(display->drm, "Port %c PLL not locked\n",
30723072
phy_name(phy));
30733073

@@ -3188,10 +3188,8 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
31883188
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
31893189

31903190
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
3191-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3192-
XELPDP_TBT_CLOCK_ACK,
3193-
XELPDP_TBT_CLOCK_ACK,
3194-
100, 0, NULL))
3191+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3192+
XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK, 100, NULL))
31953193
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
31963194
encoder->base.base.id, encoder->base.name, phy_name(phy));
31973195

@@ -3302,10 +3300,10 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
33023300
/*
33033301
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
33043302
*/
3305-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3306-
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
3307-
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
3308-
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
3303+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3304+
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
3305+
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
3306+
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
33093307
drm_warn(display->drm, "Port %c PLL not unlocked\n",
33103308
phy_name(phy));
33113309

@@ -3350,8 +3348,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
33503348
XELPDP_TBT_CLOCK_REQUEST, 0);
33513349

33523350
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
3353-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3354-
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
3351+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3352+
XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
33553353
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
33563354
encoder->base.base.id, encoder->base.name, phy_name(phy));
33573355

‎drivers/gpu/drm/i915/display/intel_ddi.c‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2577,9 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
25772577

25782578
intel_de_rmw(display, reg, 0, set_bits);
25792579

2580-
ret = intel_de_wait_custom(display, reg,
2581-
wait_bits, wait_bits,
2582-
100, 0, NULL);
2580+
ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
25832581
if (ret) {
25842582
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
25852583
port_name(port));
@@ -3079,9 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder)
30793077

30803078
intel_de_rmw(display, reg, clr_bits, 0);
30813079

3082-
ret = intel_de_wait_custom(display, reg,
3083-
wait_bits, 0,
3084-
100, 0, NULL);
3080+
ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
30853081
if (ret)
30863082
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
30873083
port_name(port));

‎drivers/gpu/drm/i915/display/intel_display_power.c‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1292,9 +1292,9 @@ static void hsw_disable_lcpll(struct intel_display *display,
12921292
val |= LCPLL_CD_SOURCE_FCLK;
12931293
intel_de_write(display, LCPLL_CTL, val);
12941294

1295-
ret = intel_de_wait_custom(display, LCPLL_CTL,
1296-
LCPLL_CD_SOURCE_FCLK_DONE, LCPLL_CD_SOURCE_FCLK_DONE,
1297-
1, 0, NULL);
1295+
ret = intel_de_wait_us(display, LCPLL_CTL,
1296+
LCPLL_CD_SOURCE_FCLK_DONE,
1297+
LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
12981298
if (ret)
12991299
drm_err(display->drm, "Switching to FCLK failed\n");
13001300

@@ -1368,9 +1368,8 @@ static void hsw_restore_lcpll(struct intel_display *display)
13681368
if (val & LCPLL_CD_SOURCE_FCLK) {
13691369
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
13701370

1371-
ret = intel_de_wait_custom(display, LCPLL_CTL,
1372-
LCPLL_CD_SOURCE_FCLK_DONE, 0,
1373-
1, 0, NULL);
1371+
ret = intel_de_wait_us(display, LCPLL_CTL,
1372+
LCPLL_CD_SOURCE_FCLK_DONE, 0, 1, NULL);
13741373
if (ret)
13751374
drm_err(display->drm,
13761375
"Switching back to LCPLL failed\n");

‎drivers/gpu/drm/i915/display/intel_dpll_mgr.c‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
20572057
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
20582058
0, PORT_PLL_POWER_ENABLE);
20592059

2060-
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2061-
PORT_PLL_POWER_STATE, PORT_PLL_POWER_STATE,
2062-
200, 0, NULL);
2060+
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2061+
PORT_PLL_POWER_STATE,
2062+
PORT_PLL_POWER_STATE, 200, NULL);
20632063
if (ret)
20642064
drm_err(display->drm,
20652065
"Power state not set for PLL:%d\n", port);
@@ -2122,9 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
21222122
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
21232123
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
21242124

2125-
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2126-
PORT_PLL_LOCK, PORT_PLL_LOCK,
2127-
200, 0, NULL);
2125+
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2126+
PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
21282127
if (ret)
21292128
drm_err(display->drm, "PLL %d not locked\n", port);
21302129

@@ -2158,9 +2157,8 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
21582157
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
21592158
PORT_PLL_POWER_ENABLE, 0);
21602159

2161-
ret = intel_de_wait_custom(display, BXT_PORT_PLL_ENABLE(port),
2162-
PORT_PLL_POWER_STATE, 0,
2163-
200, 0, NULL);
2160+
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2161+
PORT_PLL_POWER_STATE, 0, 200, NULL);
21642162
if (ret)
21652163
drm_err(display->drm,
21662164
"Power state not reset for PLL:%d\n", port);

‎drivers/gpu/drm/i915/display/intel_lt_phy.c‎

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1982,9 +1982,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
19821982
XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
19831983

19841984
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
1985-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
1986-
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
1987-
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
1985+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
1986+
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
1987+
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
19881988
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
19891989
phy_name(phy));
19901990

@@ -2089,10 +2089,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
20892089
lane_pipe_reset);
20902090

20912091
/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
2092-
if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
2093-
lane_phy_current_status,
2094-
lane_phy_current_status,
2095-
XE3PLPD_RESET_START_LATENCY_US, 0, NULL))
2092+
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2093+
lane_phy_current_status, lane_phy_current_status,
2094+
XE3PLPD_RESET_START_LATENCY_US, NULL))
20962095
drm_warn(display->drm, "PHY %c failed to reset lane\n",
20972096
phy_name(phy));
20982097

@@ -2113,9 +2112,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
21132112
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
21142113

21152114
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
2116-
if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
2117-
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
2118-
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, 0, NULL))
2115+
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
2116+
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
2117+
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
21192118
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
21202119
phy_name(phy));
21212120

‎drivers/gpu/drm/i915/display/intel_pch_refclk.c‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21,17 +21,16 @@ static void lpt_fdi_reset_mphy(struct intel_display *display)
2121

2222
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
2323

24-
ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
25-
FDI_MPHY_IOSFSB_RESET_STATUS, FDI_MPHY_IOSFSB_RESET_STATUS,
26-
100, 0, NULL);
24+
ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
25+
FDI_MPHY_IOSFSB_RESET_STATUS,
26+
FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
2727
if (ret)
2828
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
2929

3030
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
3131

32-
ret = intel_de_wait_custom(display, SOUTH_CHICKEN2,
33-
FDI_MPHY_IOSFSB_RESET_STATUS, 0,
34-
100, 0, NULL);
32+
ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
33+
FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
3534
if (ret)
3635
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
3736
}

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