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akhilpo-qcomRob Clark
akhilpo-qcom
authored and
Rob Clark
committed
drm/msm/adreno: Move adreno_gpu_func to catalogue
In A6x family (which is a pretty big one), there are separate adreno_func definitions for each sub-generations. To streamline the identification of the correct struct for a gpu, move it to the catalogue and move the gpu_init routine to struct adreno_gpu_funcs. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/689003/ Message-ID: <20251118-kaana-gpu-support-v4-6-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
1 parent f5232d6 commit 491fadb

17 files changed

Lines changed: 275 additions & 260 deletions

‎drivers/gpu/drm/msm/adreno/a2xx_catalog.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
*/
88

99
#include "adreno_gpu.h"
10+
#include "a2xx_gpu.h"
1011

1112
static const struct adreno_info a2xx_gpus[] = {
1213
{
@@ -19,7 +20,7 @@ static const struct adreno_info a2xx_gpus[] = {
1920
},
2021
.gmem = SZ_256K,
2122
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
22-
.init = a2xx_gpu_init,
23+
.funcs = &a2xx_gpu_funcs,
2324
}, { /* a200 on i.mx51 has only 128kib gmem */
2425
.chip_ids = ADRENO_CHIP_IDS(0x02000001),
2526
.family = ADRENO_2XX_GEN1,
@@ -30,7 +31,7 @@ static const struct adreno_info a2xx_gpus[] = {
3031
},
3132
.gmem = SZ_128K,
3233
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
33-
.init = a2xx_gpu_init,
34+
.funcs = &a2xx_gpu_funcs,
3435
}, {
3536
.chip_ids = ADRENO_CHIP_IDS(0x02020000),
3637
.family = ADRENO_2XX_GEN2,
@@ -41,7 +42,7 @@ static const struct adreno_info a2xx_gpus[] = {
4142
},
4243
.gmem = SZ_512K,
4344
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
44-
.init = a2xx_gpu_init,
45+
.funcs = &a2xx_gpu_funcs,
4546
}
4647
};
4748
DECLARE_ADRENO_GPULIST(a2xx);

‎drivers/gpu/drm/msm/adreno/a2xx_gpu.c‎

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -486,39 +486,18 @@ static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
486486
return ring->memptrs->rptr;
487487
}
488488

489-
static const struct adreno_gpu_funcs funcs = {
490-
.base = {
491-
.get_param = adreno_get_param,
492-
.set_param = adreno_set_param,
493-
.hw_init = a2xx_hw_init,
494-
.pm_suspend = msm_gpu_pm_suspend,
495-
.pm_resume = msm_gpu_pm_resume,
496-
.recover = a2xx_recover,
497-
.submit = a2xx_submit,
498-
.active_ring = adreno_active_ring,
499-
.irq = a2xx_irq,
500-
.destroy = a2xx_destroy,
501-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
502-
.show = adreno_show,
503-
#endif
504-
.gpu_state_get = a2xx_gpu_state_get,
505-
.gpu_state_put = adreno_gpu_state_put,
506-
.create_vm = a2xx_create_vm,
507-
.get_rptr = a2xx_get_rptr,
508-
},
509-
};
510-
511489
static const struct msm_gpu_perfcntr perfcntrs[] = {
512490
/* TODO */
513491
};
514492

515-
struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
493+
static struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
516494
{
517495
struct a2xx_gpu *a2xx_gpu = NULL;
518496
struct adreno_gpu *adreno_gpu;
519497
struct msm_gpu *gpu;
520498
struct msm_drm_private *priv = dev->dev_private;
521499
struct platform_device *pdev = priv->gpu_pdev;
500+
struct adreno_platform_config *config = pdev->dev.platform_data;
522501
int ret;
523502

524503
if (!pdev) {
@@ -539,7 +518,7 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
539518
gpu->perfcntrs = perfcntrs;
540519
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
541520

542-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
521+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
543522
if (ret)
544523
goto fail;
545524

@@ -558,3 +537,26 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev)
558537

559538
return ERR_PTR(ret);
560539
}
540+
541+
const struct adreno_gpu_funcs a2xx_gpu_funcs = {
542+
.base = {
543+
.get_param = adreno_get_param,
544+
.set_param = adreno_set_param,
545+
.hw_init = a2xx_hw_init,
546+
.pm_suspend = msm_gpu_pm_suspend,
547+
.pm_resume = msm_gpu_pm_resume,
548+
.recover = a2xx_recover,
549+
.submit = a2xx_submit,
550+
.active_ring = adreno_active_ring,
551+
.irq = a2xx_irq,
552+
.destroy = a2xx_destroy,
553+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
554+
.show = adreno_show,
555+
#endif
556+
.gpu_state_get = a2xx_gpu_state_get,
557+
.gpu_state_put = adreno_gpu_state_put,
558+
.create_vm = a2xx_create_vm,
559+
.get_rptr = a2xx_get_rptr,
560+
},
561+
.init = a2xx_gpu_init,
562+
};

‎drivers/gpu/drm/msm/adreno/a2xx_gpu.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,8 @@ struct a2xx_gpu {
1919
};
2020
#define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base)
2121

22+
extern const struct adreno_gpu_funcs a2xx_gpu_funcs;
23+
2224
struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
2325
void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
2426
dma_addr_t *tran_error);

‎drivers/gpu/drm/msm/adreno/a3xx_catalog.c‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
*/
88

99
#include "adreno_gpu.h"
10+
#include "a3xx_gpu.h"
1011

1112
static const struct adreno_info a3xx_gpus[] = {
1213
{
@@ -18,7 +19,7 @@ static const struct adreno_info a3xx_gpus[] = {
1819
},
1920
.gmem = SZ_128K,
2021
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
21-
.init = a3xx_gpu_init,
22+
.funcs = &a3xx_gpu_funcs,
2223
}, {
2324
.chip_ids = ADRENO_CHIP_IDS(0x03000520),
2425
.family = ADRENO_3XX,
@@ -29,7 +30,7 @@ static const struct adreno_info a3xx_gpus[] = {
2930
},
3031
.gmem = SZ_256K,
3132
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
32-
.init = a3xx_gpu_init,
33+
.funcs = &a3xx_gpu_funcs,
3334
}, {
3435
.chip_ids = ADRENO_CHIP_IDS(0x03000600),
3536
.family = ADRENO_3XX,
@@ -40,7 +41,7 @@ static const struct adreno_info a3xx_gpus[] = {
4041
},
4142
.gmem = SZ_128K,
4243
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
43-
.init = a3xx_gpu_init,
44+
.funcs = &a3xx_gpu_funcs,
4445
}, {
4546
.chip_ids = ADRENO_CHIP_IDS(0x03000620),
4647
.family = ADRENO_3XX,
@@ -51,7 +52,7 @@ static const struct adreno_info a3xx_gpus[] = {
5152
},
5253
.gmem = SZ_128K,
5354
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
54-
.init = a3xx_gpu_init,
55+
.funcs = &a3xx_gpu_funcs,
5556
}, {
5657
.chip_ids = ADRENO_CHIP_IDS(
5758
0x03020000,
@@ -66,7 +67,7 @@ static const struct adreno_info a3xx_gpus[] = {
6667
},
6768
.gmem = SZ_512K,
6869
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
69-
.init = a3xx_gpu_init,
70+
.funcs = &a3xx_gpu_funcs,
7071
}, {
7172
.chip_ids = ADRENO_CHIP_IDS(
7273
0x03030000,
@@ -81,7 +82,7 @@ static const struct adreno_info a3xx_gpus[] = {
8182
},
8283
.gmem = SZ_1M,
8384
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
84-
.init = a3xx_gpu_init,
85+
.funcs = &a3xx_gpu_funcs,
8586
}
8687
};
8788
DECLARE_ADRENO_GPULIST(a3xx);

‎drivers/gpu/drm/msm/adreno/a3xx_gpu.c‎

Lines changed: 27 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -508,43 +508,21 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
508508
return ring->memptrs->rptr;
509509
}
510510

511-
static const struct adreno_gpu_funcs funcs = {
512-
.base = {
513-
.get_param = adreno_get_param,
514-
.set_param = adreno_set_param,
515-
.hw_init = a3xx_hw_init,
516-
.pm_suspend = msm_gpu_pm_suspend,
517-
.pm_resume = msm_gpu_pm_resume,
518-
.recover = a3xx_recover,
519-
.submit = a3xx_submit,
520-
.active_ring = adreno_active_ring,
521-
.irq = a3xx_irq,
522-
.destroy = a3xx_destroy,
523-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
524-
.show = adreno_show,
525-
#endif
526-
.gpu_busy = a3xx_gpu_busy,
527-
.gpu_state_get = a3xx_gpu_state_get,
528-
.gpu_state_put = adreno_gpu_state_put,
529-
.create_vm = adreno_create_vm,
530-
.get_rptr = a3xx_get_rptr,
531-
},
532-
};
533-
534511
static const struct msm_gpu_perfcntr perfcntrs[] = {
535512
{ REG_A3XX_SP_PERFCOUNTER6_SELECT, REG_A3XX_RBBM_PERFCTR_SP_6_LO,
536513
SP_ALU_ACTIVE_CYCLES, "ALUACTIVE" },
537514
{ REG_A3XX_SP_PERFCOUNTER7_SELECT, REG_A3XX_RBBM_PERFCTR_SP_7_LO,
538515
SP_FS_FULL_ALU_INSTRUCTIONS, "ALUFULL" },
539516
};
540517

541-
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
518+
static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
542519
{
543520
struct a3xx_gpu *a3xx_gpu = NULL;
544521
struct adreno_gpu *adreno_gpu;
545522
struct msm_gpu *gpu;
546523
struct msm_drm_private *priv = dev->dev_private;
547524
struct platform_device *pdev = priv->gpu_pdev;
525+
struct adreno_platform_config *config = pdev->dev.platform_data;
548526
struct icc_path *ocmem_icc_path;
549527
struct icc_path *icc_path;
550528
int ret;
@@ -569,7 +547,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
569547

570548
adreno_gpu->registers = a3xx_registers;
571549

572-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
550+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
573551
if (ret)
574552
goto fail;
575553

@@ -613,3 +591,27 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
613591

614592
return ERR_PTR(ret);
615593
}
594+
595+
const struct adreno_gpu_funcs a3xx_gpu_funcs = {
596+
.base = {
597+
.get_param = adreno_get_param,
598+
.set_param = adreno_set_param,
599+
.hw_init = a3xx_hw_init,
600+
.pm_suspend = msm_gpu_pm_suspend,
601+
.pm_resume = msm_gpu_pm_resume,
602+
.recover = a3xx_recover,
603+
.submit = a3xx_submit,
604+
.active_ring = adreno_active_ring,
605+
.irq = a3xx_irq,
606+
.destroy = a3xx_destroy,
607+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
608+
.show = adreno_show,
609+
#endif
610+
.gpu_busy = a3xx_gpu_busy,
611+
.gpu_state_get = a3xx_gpu_state_get,
612+
.gpu_state_put = adreno_gpu_state_put,
613+
.create_vm = adreno_create_vm,
614+
.get_rptr = a3xx_get_rptr,
615+
},
616+
.init = a3xx_gpu_init,
617+
};

‎drivers/gpu/drm/msm/adreno/a3xx_gpu.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,4 +23,6 @@ struct a3xx_gpu {
2323
};
2424
#define to_a3xx_gpu(x) container_of(x, struct a3xx_gpu, base)
2525

26+
extern const struct adreno_gpu_funcs a3xx_gpu_funcs;
27+
2628
#endif /* __A3XX_GPU_H__ */

‎drivers/gpu/drm/msm/adreno/a4xx_catalog.c‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
*/
88

99
#include "adreno_gpu.h"
10+
#include "a4xx_gpu.h"
1011

1112
static const struct adreno_info a4xx_gpus[] = {
1213
{
@@ -19,7 +20,7 @@ static const struct adreno_info a4xx_gpus[] = {
1920
},
2021
.gmem = SZ_256K,
2122
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
22-
.init = a4xx_gpu_init,
23+
.funcs = &a4xx_gpu_funcs,
2324
}, {
2425
.chip_ids = ADRENO_CHIP_IDS(0x04020000),
2526
.family = ADRENO_4XX,
@@ -30,7 +31,7 @@ static const struct adreno_info a4xx_gpus[] = {
3031
},
3132
.gmem = (SZ_1M + SZ_512K),
3233
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
33-
.init = a4xx_gpu_init,
34+
.funcs = &a4xx_gpu_funcs,
3435
}, {
3536
.chip_ids = ADRENO_CHIP_IDS(0x04030002),
3637
.family = ADRENO_4XX,
@@ -41,7 +42,7 @@ static const struct adreno_info a4xx_gpus[] = {
4142
},
4243
.gmem = (SZ_1M + SZ_512K),
4344
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
44-
.init = a4xx_gpu_init,
45+
.funcs = &a4xx_gpu_funcs,
4546
}
4647
};
4748
DECLARE_ADRENO_GPULIST(a4xx);

‎drivers/gpu/drm/msm/adreno/a4xx_gpu.c‎

Lines changed: 28 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -627,37 +627,14 @@ static u32 a4xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
627627
return ring->memptrs->rptr;
628628
}
629629

630-
static const struct adreno_gpu_funcs funcs = {
631-
.base = {
632-
.get_param = adreno_get_param,
633-
.set_param = adreno_set_param,
634-
.hw_init = a4xx_hw_init,
635-
.pm_suspend = a4xx_pm_suspend,
636-
.pm_resume = a4xx_pm_resume,
637-
.recover = a4xx_recover,
638-
.submit = a4xx_submit,
639-
.active_ring = adreno_active_ring,
640-
.irq = a4xx_irq,
641-
.destroy = a4xx_destroy,
642-
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
643-
.show = adreno_show,
644-
#endif
645-
.gpu_busy = a4xx_gpu_busy,
646-
.gpu_state_get = a4xx_gpu_state_get,
647-
.gpu_state_put = adreno_gpu_state_put,
648-
.create_vm = adreno_create_vm,
649-
.get_rptr = a4xx_get_rptr,
650-
},
651-
.get_timestamp = a4xx_get_timestamp,
652-
};
653-
654-
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
630+
static struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
655631
{
656632
struct a4xx_gpu *a4xx_gpu = NULL;
657633
struct adreno_gpu *adreno_gpu;
658634
struct msm_gpu *gpu;
659635
struct msm_drm_private *priv = dev->dev_private;
660636
struct platform_device *pdev = priv->gpu_pdev;
637+
struct adreno_platform_config *config = pdev->dev.platform_data;
661638
struct icc_path *ocmem_icc_path;
662639
struct icc_path *icc_path;
663640
int ret;
@@ -680,7 +657,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
680657
gpu->perfcntrs = NULL;
681658
gpu->num_perfcntrs = 0;
682659

683-
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
660+
ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, 1);
684661
if (ret)
685662
goto fail;
686663

@@ -726,3 +703,28 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
726703

727704
return ERR_PTR(ret);
728705
}
706+
707+
const struct adreno_gpu_funcs a4xx_gpu_funcs = {
708+
.base = {
709+
.get_param = adreno_get_param,
710+
.set_param = adreno_set_param,
711+
.hw_init = a4xx_hw_init,
712+
.pm_suspend = a4xx_pm_suspend,
713+
.pm_resume = a4xx_pm_resume,
714+
.recover = a4xx_recover,
715+
.submit = a4xx_submit,
716+
.active_ring = adreno_active_ring,
717+
.irq = a4xx_irq,
718+
.destroy = a4xx_destroy,
719+
#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
720+
.show = adreno_show,
721+
#endif
722+
.gpu_busy = a4xx_gpu_busy,
723+
.gpu_state_get = a4xx_gpu_state_get,
724+
.gpu_state_put = adreno_gpu_state_put,
725+
.create_vm = adreno_create_vm,
726+
.get_rptr = a4xx_get_rptr,
727+
},
728+
.init = a4xx_gpu_init,
729+
.get_timestamp = a4xx_get_timestamp,
730+
};

‎drivers/gpu/drm/msm/adreno/a4xx_gpu.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,4 +20,6 @@ struct a4xx_gpu {
2020
};
2121
#define to_a4xx_gpu(x) container_of(x, struct a4xx_gpu, base)
2222

23+
extern const struct adreno_gpu_funcs a4xx_gpu_funcs;
24+
2325
#endif /* __A4XX_GPU_H__ */

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