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uiopauboakemnadegoldelico
authored and
Linus Walleij
committed
pinctrl: ingenic: add x1600 support
Add support for the Lumissil/Ingenic X1600 SoC. It uses shadow registers to commit changes to multiple pinctrl registers in parallel. Define specific Chip ID, register offsets, pin tables etc. Handling the unique X1600_GPIO_PU only for the x1600 but not for x1830 and above must be carefully taken into account. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Co-authored-by: Andreas Kemnade <andreas@kemnade.info> Co-authored-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/84477ec9cb9ed13bf4f6f87d5fb3b55542d31097.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Lines changed: 242 additions & 2 deletions

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‎drivers/pinctrl/pinctrl-ingenic.c‎

Lines changed: 242 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
* Ingenic SoCs pinctrl driver
44
*
55
* Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
6-
* Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
6+
* Copyright (c) 2017, 2019, 2020, 2023 Paul Boddie <paul@boddie.org.uk>
77
* Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
88
*/
99

@@ -58,6 +58,8 @@
5858
#define JZ4770_GPIO_FLAG 0x50
5959
#define JZ4770_GPIO_PEN 0x70
6060

61+
#define X1600_GPIO_PU 0x80
62+
6163
#define X1830_GPIO_PEL 0x110
6264
#define X1830_GPIO_PEH 0x120
6365
#define X1830_GPIO_SR 0x150
@@ -112,6 +114,7 @@ enum jz_version {
112114
ID_JZ4780,
113115
ID_X1000,
114116
ID_X1500,
117+
ID_X1600,
115118
ID_X1830,
116119
ID_X2000,
117120
ID_X2100,
@@ -162,6 +165,7 @@ static const unsigned long enabled_socs =
162165
IS_ENABLED(CONFIG_MACH_JZ4780) << ID_JZ4780 |
163166
IS_ENABLED(CONFIG_MACH_X1000) << ID_X1000 |
164167
IS_ENABLED(CONFIG_MACH_X1500) << ID_X1500 |
168+
IS_ENABLED(CONFIG_MACH_X1600) << ID_X1600 |
165169
IS_ENABLED(CONFIG_MACH_X1830) << ID_X1830 |
166170
IS_ENABLED(CONFIG_MACH_X2000) << ID_X2000 |
167171
IS_ENABLED(CONFIG_MACH_X2100) << ID_X2100;
@@ -2351,6 +2355,233 @@ static const struct ingenic_chip_info x1500_chip_info = {
23512355
.access_table = &x1000_access_table,
23522356
};
23532357

2358+
static const u32 x1600_pull_ups[4] = {
2359+
0xffffffff, 0xdffbf7bf, 0x987e0000, 0x0000003f,
2360+
};
2361+
2362+
static const u32 x1600_pull_downs[4] = {
2363+
0x00000000, 0x00000000, 0x07000007, 0x00000000,
2364+
};
2365+
2366+
static int x1600_uart0_data_pins[] = { 0x27, 0x28, };
2367+
static int x1600_uart0_hwflow_pins[] = { 0x29, 0x2a, };
2368+
static int x1600_uart1_data_pins[] = { 0x23, 0x22, };
2369+
static int x1600_uart1_hwflow_pins[] = { 0x25, 0x24, };
2370+
static int x1600_uart2_data_a_pins[] = { 0x1f, 0x1e, };
2371+
static int x1600_uart2_data_b_pins[] = { 0x21, 0x20, };
2372+
static int x1600_uart3_data_b_pins[] = { 0x25, 0x24, };
2373+
static int x1600_uart3_data_d_pins[] = { 0x65, 0x64, };
2374+
static int x1600_sfc_pins[] = { 0x53, 0x54, 0x55, 0x56, 0x51, 0x52, 0x24, };
2375+
static int x1600_ssi_dt_a_pins[] = { 0x1e, };
2376+
static int x1600_ssi_dt_b_pins[] = { 0x2d, };
2377+
static int x1600_ssi_dr_a_pins[] = { 0x1d, };
2378+
static int x1600_ssi_dr_b_pins[] = { 0x2e, };
2379+
static int x1600_ssi_clk_a_pins[] = { 0x1f, };
2380+
static int x1600_ssi_clk_b_pins[] = { 0x2c, };
2381+
static int x1600_ssi_ce0_a_pins[] = { 0x1c, };
2382+
static int x1600_ssi_ce0_b_pins[] = { 0x31, };
2383+
static int x1600_ssi_ce1_a_pins[] = { 0x22, };
2384+
static int x1600_ssi_ce1_b_pins[] = { 0x30, };
2385+
static int x1600_mmc0_1bit_b_pins[] = { 0x2c, 0x2d, 0x2e, };
2386+
static int x1600_mmc0_4bit_b_pins[] = { 0x2f, 0x30, 0x31, };
2387+
static int x1600_mmc0_1bit_c_pins[] = { 0x51, 0x53, 0x54, };
2388+
static int x1600_mmc0_4bit_c_pins[] = { 0x56, 0x55, 0x52, };
2389+
static int x1600_mmc1_1bit_pins[] = { 0x60, 0x61, 0x62, };
2390+
static int x1600_mmc1_4bit_pins[] = { 0x63, 0x64, 0x65, };
2391+
static int x1600_i2c0_a_pins[] = { 0x1d, 0x1c, };
2392+
static int x1600_i2c0_b_pins[] = { 0x3f, 0x3e, };
2393+
static int x1600_i2c1_b_15_pins[] = { 0x30, 0x2f, };
2394+
static int x1600_i2c1_b_19_pins[] = { 0x34, 0x33, };
2395+
static int x1600_i2s_data_tx_pins[] = { 0x39, };
2396+
static int x1600_i2s_data_rx_pins[] = { 0x35, };
2397+
static int x1600_i2s_clk_rx_pins[] = { 0x37, 0x38, };
2398+
static int x1600_i2s_clk_tx_pins[] = { 0x3b, 0x3c, };
2399+
static int x1600_i2s_sysclk_pins[] = { 0x36, 0x3a, };
2400+
2401+
static int x1600_cim_pins[] = {
2402+
0x14, 0x16, 0x15, 0x18, 0x13,
2403+
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2404+
};
2405+
2406+
static int x1600_slcd_8bit_pins[] = {
2407+
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2408+
0x17, 0x19, 0x1a, 0x1b,
2409+
};
2410+
2411+
static int x1600_slcd_16bit_pins[] = {
2412+
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2413+
};
2414+
2415+
static int x1600_lcd_16bit_pins[] = {
2416+
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2417+
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2418+
0x18, 0x19, 0x1a, 0x1b,
2419+
};
2420+
2421+
static int x1600_lcd_18bit_pins[] = {
2422+
0x10, 0x11,
2423+
};
2424+
2425+
static int x1600_lcd_24bit_pins[] = {
2426+
0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
2427+
};
2428+
2429+
static int x1600_pwm_pwm0_pins[] = { 0x40, };
2430+
static int x1600_pwm_pwm1_pins[] = { 0x41, };
2431+
static int x1600_pwm_pwm2_pins[] = { 0x42, };
2432+
static int x1600_pwm_pwm3_pins[] = { 0x58, };
2433+
static int x1600_pwm_pwm4_pins[] = { 0x59, };
2434+
static int x1600_pwm_pwm5_b_pins[] = { 0x33, };
2435+
static int x1600_pwm_pwm5_c_pins[] = { 0x5a, };
2436+
static int x1600_pwm_pwm6_b9_pins[] = { 0x29, };
2437+
static int x1600_pwm_pwm6_b20_pins[] = { 0x34, };
2438+
static int x1600_pwm_pwm7_b10_pins[] = { 0x2a, };
2439+
static int x1600_pwm_pwm7_b21_pins[] = { 0x35, };
2440+
2441+
static int x1600_mac_pins[] = {
2442+
0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c,
2443+
};
2444+
2445+
static int x1600_sfc_funcs[] = { 0, 0, 0, 0, 0, 0, 2, };
2446+
2447+
static const struct group_desc x1600_groups[] = {
2448+
INGENIC_PIN_GROUP("uart0-data", x1600_uart0_data, 0),
2449+
INGENIC_PIN_GROUP("uart0-hwflow", x1600_uart0_hwflow, 0),
2450+
INGENIC_PIN_GROUP("uart1-data", x1600_uart1_data, 1),
2451+
INGENIC_PIN_GROUP("uart1-hwflow", x1600_uart1_hwflow, 1),
2452+
INGENIC_PIN_GROUP("uart2-data-a", x1600_uart2_data_a, 2),
2453+
INGENIC_PIN_GROUP("uart2-data-b", x1600_uart2_data_b, 1),
2454+
INGENIC_PIN_GROUP("uart3-data-b", x1600_uart3_data_b, 0),
2455+
INGENIC_PIN_GROUP("uart3-data-d", x1600_uart3_data_d, 2),
2456+
INGENIC_PIN_GROUP_FUNCS("sfc", x1600_sfc, x1600_sfc_funcs),
2457+
INGENIC_PIN_GROUP("ssi-dt-a", x1600_ssi_dt_a, 0),
2458+
INGENIC_PIN_GROUP("ssi-dt-b", x1600_ssi_dt_b, 1),
2459+
INGENIC_PIN_GROUP("ssi-dr-a", x1600_ssi_dr_a, 0),
2460+
INGENIC_PIN_GROUP("ssi-dr-b", x1600_ssi_dr_b, 1),
2461+
INGENIC_PIN_GROUP("ssi-clk-a", x1600_ssi_clk_a, 0),
2462+
INGENIC_PIN_GROUP("ssi-clk-b", x1600_ssi_clk_b, 1),
2463+
INGENIC_PIN_GROUP("ssi-ce0-a", x1600_ssi_ce0_a, 0),
2464+
INGENIC_PIN_GROUP("ssi-ce0-b", x1600_ssi_ce0_b, 1),
2465+
INGENIC_PIN_GROUP("ssi-ce1-a", x1600_ssi_ce1_a, 2),
2466+
INGENIC_PIN_GROUP("ssi-ce1-b", x1600_ssi_ce1_b, 1),
2467+
INGENIC_PIN_GROUP("mmc0-1bit-b", x1600_mmc0_1bit_b, 0),
2468+
INGENIC_PIN_GROUP("mmc0-4bit-b", x1600_mmc0_4bit_b, 0),
2469+
INGENIC_PIN_GROUP("mmc0-1bit-c", x1600_mmc0_1bit_c, 1),
2470+
INGENIC_PIN_GROUP("mmc0-4bit-c", x1600_mmc0_4bit_c, 1),
2471+
INGENIC_PIN_GROUP("mmc1-1bit", x1600_mmc1_1bit, 0),
2472+
INGENIC_PIN_GROUP("mmc1-4bit", x1600_mmc1_4bit, 0),
2473+
INGENIC_PIN_GROUP("i2c0-data-a", x1600_i2c0_a, 2),
2474+
INGENIC_PIN_GROUP("i2c0-data-b", x1600_i2c0_b, 0),
2475+
INGENIC_PIN_GROUP("i2c1-data-b-15", x1600_i2c1_b_15, 2),
2476+
INGENIC_PIN_GROUP("i2c1-data-b-19", x1600_i2c1_b_19, 0),
2477+
INGENIC_PIN_GROUP("i2s-data-tx", x1600_i2s_data_tx, 0),
2478+
INGENIC_PIN_GROUP("i2s-data-rx", x1600_i2s_data_rx, 0),
2479+
INGENIC_PIN_GROUP("i2s-clk-rx", x1600_i2s_clk_rx, 0),
2480+
INGENIC_PIN_GROUP("i2s-clk-tx", x1600_i2s_clk_tx, 0),
2481+
INGENIC_PIN_GROUP("i2s-sysclk", x1600_i2s_sysclk, 0),
2482+
INGENIC_PIN_GROUP("cim-data", x1600_cim, 2),
2483+
INGENIC_PIN_GROUP("slcd-8bit", x1600_slcd_8bit, 1),
2484+
INGENIC_PIN_GROUP("slcd-16bit", x1600_slcd_16bit, 1),
2485+
INGENIC_PIN_GROUP("lcd-16bit", x1600_lcd_16bit, 0),
2486+
INGENIC_PIN_GROUP("lcd-18bit", x1600_lcd_18bit, 0),
2487+
INGENIC_PIN_GROUP("lcd-24bit", x1600_lcd_24bit, 0),
2488+
INGENIC_PIN_GROUP("pwm0", x1600_pwm_pwm0, 0),
2489+
INGENIC_PIN_GROUP("pwm1", x1600_pwm_pwm1, 0),
2490+
INGENIC_PIN_GROUP("pwm2", x1600_pwm_pwm2, 0),
2491+
INGENIC_PIN_GROUP("pwm3", x1600_pwm_pwm3, 1),
2492+
INGENIC_PIN_GROUP("pwm4", x1600_pwm_pwm4, 1),
2493+
INGENIC_PIN_GROUP("pwm5-b", x1600_pwm_pwm5_b, 2),
2494+
INGENIC_PIN_GROUP("pwm5-c", x1600_pwm_pwm5_c, 1),
2495+
INGENIC_PIN_GROUP("pwm6-b9", x1600_pwm_pwm6_b9, 1),
2496+
INGENIC_PIN_GROUP("pwm6-b20", x1600_pwm_pwm6_b20, 2),
2497+
INGENIC_PIN_GROUP("pwm7-b10", x1600_pwm_pwm7_b10, 1),
2498+
INGENIC_PIN_GROUP("pwm7-b21", x1600_pwm_pwm7_b21, 2),
2499+
INGENIC_PIN_GROUP("mac", x1600_mac, 1),
2500+
};
2501+
2502+
static const char * const x1600_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2503+
static const char * const x1600_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2504+
static const char * const x1600_uart2_groups[] = { "uart2-data-a", "uart2-data-b", };
2505+
static const char * const x1600_uart3_groups[] = { "uart3-data-b", "uart3-data-d", };
2506+
2507+
static const char * const x1600_sfc_groups[] = { "sfc", };
2508+
2509+
static const char * const x1600_ssi_groups[] = {
2510+
"ssi-dt-a", "ssi-dt-b",
2511+
"ssi-dr-a", "ssi-dr-b",
2512+
"ssi-clk-a", "ssi-clk-b",
2513+
"ssi-ce0-a", "ssi-ce0-b",
2514+
"ssi-ce1-a", "ssi-ce1-b",
2515+
};
2516+
2517+
static const char * const x1600_mmc0_groups[] = { "mmc0-1bit-b", "mmc0-4bit-b",
2518+
"mmc0-1bit-c", "mmc0-4bit-c",
2519+
};
2520+
2521+
static const char * const x1600_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2522+
2523+
static const char * const x1600_i2c0_groups[] = { "i2c0-data-a", "i2c0-data-b", };
2524+
static const char * const x1600_i2c1_groups[] = { "i2c1-data-b-15", "i2c1-data-b-19", };
2525+
2526+
static const char * const x1600_i2s_groups[] = {
2527+
"i2s-data-tx", "i2s-data-rx", "i2s-clk-rx", "i2s-clk-tx", "i2s-sysclk",
2528+
};
2529+
2530+
static const char * const x1600_cim_groups[] = { "cim-data", };
2531+
2532+
static const char * const x1600_lcd_groups[] = { "slcd-8bit", "slcd-16bit",
2533+
"lcd-16bit", "lcd-18bit", "lcd-24bit", "lcd-no-pins",
2534+
};
2535+
2536+
static const char * const x1600_pwm0_groups[] = { "pwm0", };
2537+
static const char * const x1600_pwm1_groups[] = { "pwm1", };
2538+
static const char * const x1600_pwm2_groups[] = { "pwm2", };
2539+
static const char * const x1600_pwm3_groups[] = { "pwm3", };
2540+
static const char * const x1600_pwm4_groups[] = { "pwm4", };
2541+
static const char * const x1600_pwm5_groups[] = { "pwm5-b", "pwm5-c", };
2542+
static const char * const x1600_pwm6_groups[] = { "pwm6-b9", "pwm6-b20", };
2543+
static const char * const x1600_pwm7_groups[] = { "pwm7-b10", "pwm7-b21", };
2544+
2545+
static const char * const x1600_mac_groups[] = { "mac", };
2546+
2547+
static const struct function_desc x1600_functions[] = {
2548+
INGENIC_PIN_FUNCTION("uart0", x1600_uart0),
2549+
INGENIC_PIN_FUNCTION("uart1", x1600_uart1),
2550+
INGENIC_PIN_FUNCTION("uart2", x1600_uart2),
2551+
INGENIC_PIN_FUNCTION("uart3", x1600_uart3),
2552+
INGENIC_PIN_FUNCTION("sfc", x1600_sfc),
2553+
INGENIC_PIN_FUNCTION("ssi", x1600_ssi),
2554+
INGENIC_PIN_FUNCTION("mmc0", x1600_mmc0),
2555+
INGENIC_PIN_FUNCTION("mmc1", x1600_mmc1),
2556+
INGENIC_PIN_FUNCTION("i2c0", x1600_i2c0),
2557+
INGENIC_PIN_FUNCTION("i2c1", x1600_i2c1),
2558+
INGENIC_PIN_FUNCTION("i2s", x1600_i2s),
2559+
INGENIC_PIN_FUNCTION("cim", x1600_cim),
2560+
INGENIC_PIN_FUNCTION("lcd", x1600_lcd),
2561+
INGENIC_PIN_FUNCTION("pwm0", x1600_pwm0),
2562+
INGENIC_PIN_FUNCTION("pwm1", x1600_pwm1),
2563+
INGENIC_PIN_FUNCTION("pwm2", x1600_pwm2),
2564+
INGENIC_PIN_FUNCTION("pwm3", x1600_pwm3),
2565+
INGENIC_PIN_FUNCTION("pwm4", x1600_pwm4),
2566+
INGENIC_PIN_FUNCTION("pwm5", x1600_pwm5),
2567+
INGENIC_PIN_FUNCTION("pwm6", x1600_pwm6),
2568+
INGENIC_PIN_FUNCTION("pwm7", x1600_pwm7),
2569+
INGENIC_PIN_FUNCTION("mac", x1600_mac),
2570+
};
2571+
2572+
static const struct ingenic_chip_info x1600_chip_info = {
2573+
.num_chips = 4,
2574+
.reg_offset = 0x100,
2575+
.version = ID_X1600,
2576+
.groups = x1600_groups,
2577+
.num_groups = ARRAY_SIZE(x1600_groups),
2578+
.functions = x1600_functions,
2579+
.num_functions = ARRAY_SIZE(x1600_functions),
2580+
.pull_ups = x1600_pull_ups,
2581+
.pull_downs = x1600_pull_downs,
2582+
.access_table = &x1000_access_table,
2583+
};
2584+
23542585
static const u32 x1830_pull_ups[4] = {
23552586
0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
23562587
};
@@ -3860,7 +4091,9 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
38604091
pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
38614092

38624093
} else {
3863-
if (is_soc_or_above(jzpc, ID_JZ4770))
4094+
if (is_soc_or_above(jzpc, ID_X1600))
4095+
pull = ingenic_get_pin_config(jzpc, pin, X1600_GPIO_PU);
4096+
else if (is_soc_or_above(jzpc, ID_JZ4770))
38644097
pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
38654098
else if (is_soc_or_above(jzpc, ID_JZ4740))
38664099
pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
@@ -3959,6 +4192,8 @@ static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
39594192
REG_SET(X1830_GPIO_PEH), bias << idxh);
39604193
}
39614194

4195+
} else if (is_soc_or_above(jzpc, ID_X1600)) {
4196+
ingenic_config_pin(jzpc, pin, X1600_GPIO_PU, bias);
39624197
} else if (is_soc_or_above(jzpc, ID_JZ4770)) {
39634198
ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
39644199
} else if (is_soc_or_above(jzpc, ID_JZ4740)) {
@@ -4150,6 +4385,7 @@ static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
41504385
{ .compatible = "ingenic,jz4775-gpio" },
41514386
{ .compatible = "ingenic,jz4780-gpio" },
41524387
{ .compatible = "ingenic,x1000-gpio" },
4388+
{ .compatible = "ingenic,x1600-gpio" },
41534389
{ .compatible = "ingenic,x1830-gpio" },
41544390
{ .compatible = "ingenic,x2000-gpio" },
41554391
{ .compatible = "ingenic,x2100-gpio" },
@@ -4397,6 +4633,10 @@ static const struct of_device_id ingenic_pinctrl_of_matches[] = {
43974633
.compatible = "ingenic,x1500-pinctrl",
43984634
.data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
43994635
},
4636+
{
4637+
.compatible = "ingenic,x1600-pinctrl",
4638+
.data = IF_ENABLED(CONFIG_MACH_X1600, &x1600_chip_info)
4639+
},
44004640
{
44014641
.compatible = "ingenic,x1830-pinctrl",
44024642
.data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)

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