|
2683 | 2683 | */ |
2684 | 2684 | }; |
2685 | 2685 | }; |
| 2686 | + |
| 2687 | + mcasp0: mcasp@2b00000 { |
| 2688 | + compatible = "ti,am33xx-mcasp-audio"; |
| 2689 | + reg = <0x00 0x02b00000 0x00 0x2000>, |
| 2690 | + <0x00 0x02b08000 0x00 0x1000>; |
| 2691 | + reg-names = "mpu","dat"; |
| 2692 | + interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, |
| 2693 | + <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; |
| 2694 | + interrupt-names = "tx", "rx"; |
| 2695 | + dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; |
| 2696 | + dma-names = "tx", "rx"; |
| 2697 | + clocks = <&k3_clks 265 0>; |
| 2698 | + clock-names = "fck"; |
| 2699 | + assigned-clocks = <&k3_clks 265 0>; |
| 2700 | + assigned-clock-parents = <&k3_clks 265 1>; |
| 2701 | + power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; |
| 2702 | + status = "disabled"; |
| 2703 | + }; |
| 2704 | + |
| 2705 | + mcasp1: mcasp@2b10000 { |
| 2706 | + compatible = "ti,am33xx-mcasp-audio"; |
| 2707 | + reg = <0x00 0x02b10000 0x00 0x2000>, |
| 2708 | + <0x00 0x02b18000 0x00 0x1000>; |
| 2709 | + reg-names = "mpu","dat"; |
| 2710 | + interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, |
| 2711 | + <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; |
| 2712 | + interrupt-names = "tx", "rx"; |
| 2713 | + dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; |
| 2714 | + dma-names = "tx", "rx"; |
| 2715 | + clocks = <&k3_clks 266 0>; |
| 2716 | + clock-names = "fck"; |
| 2717 | + assigned-clocks = <&k3_clks 266 0>; |
| 2718 | + assigned-clock-parents = <&k3_clks 266 1>; |
| 2719 | + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; |
| 2720 | + status = "disabled"; |
| 2721 | + }; |
| 2722 | + |
| 2723 | + mcasp2: mcasp@2b20000 { |
| 2724 | + compatible = "ti,am33xx-mcasp-audio"; |
| 2725 | + reg = <0x00 0x02b20000 0x00 0x2000>, |
| 2726 | + <0x00 0x02b28000 0x00 0x1000>; |
| 2727 | + reg-names = "mpu","dat"; |
| 2728 | + interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, |
| 2729 | + <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; |
| 2730 | + interrupt-names = "tx", "rx"; |
| 2731 | + dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; |
| 2732 | + dma-names = "tx", "rx"; |
| 2733 | + clocks = <&k3_clks 267 0>; |
| 2734 | + clock-names = "fck"; |
| 2735 | + assigned-clocks = <&k3_clks 267 0>; |
| 2736 | + assigned-clock-parents = <&k3_clks 267 1>; |
| 2737 | + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; |
| 2738 | + status = "disabled"; |
| 2739 | + }; |
| 2740 | + |
| 2741 | + mcasp3: mcasp@2b30000 { |
| 2742 | + compatible = "ti,am33xx-mcasp-audio"; |
| 2743 | + reg = <0x00 0x02b30000 0x00 0x2000>, |
| 2744 | + <0x00 0x02b38000 0x00 0x1000>; |
| 2745 | + reg-names = "mpu","dat"; |
| 2746 | + interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, |
| 2747 | + <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; |
| 2748 | + interrupt-names = "tx", "rx"; |
| 2749 | + dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; |
| 2750 | + dma-names = "tx", "rx"; |
| 2751 | + clocks = <&k3_clks 268 0>; |
| 2752 | + clock-names = "fck"; |
| 2753 | + assigned-clocks = <&k3_clks 268 0>; |
| 2754 | + assigned-clock-parents = <&k3_clks 268 1>; |
| 2755 | + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; |
| 2756 | + status = "disabled"; |
| 2757 | + }; |
| 2758 | + |
| 2759 | + mcasp4: mcasp@2b40000 { |
| 2760 | + compatible = "ti,am33xx-mcasp-audio"; |
| 2761 | + reg = <0x00 0x02b40000 0x00 0x2000>, |
| 2762 | + <0x00 0x02b48000 0x00 0x1000>; |
| 2763 | + reg-names = "mpu","dat"; |
| 2764 | + interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, |
| 2765 | + <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; |
| 2766 | + interrupt-names = "tx", "rx"; |
| 2767 | + dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>; |
| 2768 | + dma-names = "tx", "rx"; |
| 2769 | + clocks = <&k3_clks 269 0>; |
| 2770 | + clock-names = "fck"; |
| 2771 | + assigned-clocks = <&k3_clks 269 0>; |
| 2772 | + assigned-clock-parents = <&k3_clks 269 1>; |
| 2773 | + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; |
| 2774 | + status = "disabled"; |
| 2775 | + }; |
2686 | 2776 | }; |
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