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dt-bindings: display: Correct indentation and style in DTS example
DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # msm Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Link: https://lore.kernel.org/r/20250107125854.227233-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
1 parent 5f42297 commit 52659fa

12 files changed

Lines changed: 243 additions & 244 deletions

‎Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -148,10 +148,10 @@ examples:
148148
149149
/* TMDS Output */
150150
hdmi_tx_tmds_port: port@1 {
151-
reg = <1>;
151+
reg = <1>;
152152
153-
hdmi_tx_tmds_out: endpoint {
154-
remote-endpoint = <&hdmi_connector_in>;
155-
};
153+
hdmi_tx_tmds_out: endpoint {
154+
remote-endpoint = <&hdmi_connector_in>;
155+
};
156156
};
157157
};

‎Documentation/devicetree/bindings/display/bridge/fsl,imx8mp-hdmi-tx.yaml‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -82,21 +82,21 @@ examples:
8282
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
8383
reg-io-width = <1>;
8484
ports {
85-
#address-cells = <1>;
86-
#size-cells = <0>;
87-
port@0 {
88-
reg = <0>;
89-
90-
hdmi_tx_from_pvi: endpoint {
91-
remote-endpoint = <&pvi_to_hdmi_tx>;
92-
};
93-
};
94-
95-
port@1 {
96-
reg = <1>;
97-
hdmi_tx_out: endpoint {
98-
remote-endpoint = <&hdmi0_con>;
99-
};
100-
};
85+
#address-cells = <1>;
86+
#size-cells = <0>;
87+
port@0 {
88+
reg = <0>;
89+
90+
endpoint {
91+
remote-endpoint = <&pvi_to_hdmi_tx>;
92+
};
93+
};
94+
95+
port@1 {
96+
reg = <1>;
97+
endpoint {
98+
remote-endpoint = <&hdmi0_con>;
99+
};
100+
};
101101
};
102102
};

‎Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -243,40 +243,40 @@ examples:
243243
#include <dt-bindings/interrupt-controller/arm-gic.h>
244244
245245
dsi@13900000 {
246-
compatible = "samsung,exynos5433-mipi-dsi";
247-
reg = <0x13900000 0xC0>;
248-
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
249-
phys = <&mipi_phy 1>;
250-
phy-names = "dsim";
251-
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
252-
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
253-
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
254-
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
255-
<&cmu_disp CLK_SCLK_DSIM0>;
256-
clock-names = "bus_clk",
257-
"phyclk_mipidphy0_bitclkdiv8",
258-
"phyclk_mipidphy0_rxclkesc0",
259-
"sclk_rgb_vclk_to_dsim0",
260-
"sclk_mipi";
261-
power-domains = <&pd_disp>;
262-
vddcore-supply = <&ldo6_reg>;
263-
vddio-supply = <&ldo7_reg>;
264-
samsung,burst-clock-frequency = <512000000>;
265-
samsung,esc-clock-frequency = <16000000>;
266-
samsung,pll-clock-frequency = <24000000>;
267-
pinctrl-names = "default";
268-
pinctrl-0 = <&te_irq>;
269-
270-
ports {
271-
#address-cells = <1>;
272-
#size-cells = <0>;
273-
274-
port@0 {
275-
reg = <0>;
276-
277-
dsi_to_mic: endpoint {
278-
remote-endpoint = <&mic_to_dsi>;
279-
};
280-
};
281-
};
246+
compatible = "samsung,exynos5433-mipi-dsi";
247+
reg = <0x13900000 0xC0>;
248+
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
249+
phys = <&mipi_phy 1>;
250+
phy-names = "dsim";
251+
clocks = <&cmu_disp CLK_PCLK_DSIM0>,
252+
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
253+
<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
254+
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
255+
<&cmu_disp CLK_SCLK_DSIM0>;
256+
clock-names = "bus_clk",
257+
"phyclk_mipidphy0_bitclkdiv8",
258+
"phyclk_mipidphy0_rxclkesc0",
259+
"sclk_rgb_vclk_to_dsim0",
260+
"sclk_mipi";
261+
power-domains = <&pd_disp>;
262+
vddcore-supply = <&ldo6_reg>;
263+
vddio-supply = <&ldo7_reg>;
264+
samsung,burst-clock-frequency = <512000000>;
265+
samsung,esc-clock-frequency = <16000000>;
266+
samsung,pll-clock-frequency = <24000000>;
267+
pinctrl-names = "default";
268+
pinctrl-0 = <&te_irq>;
269+
270+
ports {
271+
#address-cells = <1>;
272+
#size-cells = <0>;
273+
274+
port@0 {
275+
reg = <0>;
276+
277+
dsi_to_mic: endpoint {
278+
remote-endpoint = <&mic_to_dsi>;
279+
};
280+
};
281+
};
282282
};

‎Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -104,30 +104,30 @@ examples:
104104
#size-cells = <2>;
105105
106106
aal@14015000 {
107-
compatible = "mediatek,mt8173-disp-aal";
108-
reg = <0 0x14015000 0 0x1000>;
109-
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
110-
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
111-
clocks = <&mmsys CLK_MM_DISP_AAL>;
112-
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
113-
114-
ports {
115-
#address-cells = <1>;
116-
#size-cells = <0>;
117-
118-
port@0 {
119-
reg = <0>;
120-
aal0_in: endpoint {
121-
remote-endpoint = <&ccorr0_out>;
122-
};
123-
};
124-
125-
port@1 {
126-
reg = <1>;
127-
aal0_out: endpoint {
128-
remote-endpoint = <&gamma0_in>;
129-
};
130-
};
131-
};
132-
};
107+
compatible = "mediatek,mt8173-disp-aal";
108+
reg = <0 0x14015000 0 0x1000>;
109+
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
110+
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
111+
clocks = <&mmsys CLK_MM_DISP_AAL>;
112+
mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
113+
114+
ports {
115+
#address-cells = <1>;
116+
#size-cells = <0>;
117+
118+
port@0 {
119+
reg = <0>;
120+
endpoint {
121+
remote-endpoint = <&ccorr0_out>;
122+
};
123+
};
124+
125+
port@1 {
126+
reg = <1>;
127+
endpoint {
128+
remote-endpoint = <&gamma0_in>;
129+
};
130+
};
131+
};
132+
};
133133
};

‎Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml‎

Lines changed: 59 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -416,63 +416,63 @@ unevaluatedProperties: false
416416

417417
examples:
418418
- |
419-
#include <dt-bindings/interrupt-controller/arm-gic.h>
420-
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
421-
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
422-
#include <dt-bindings/power/qcom-rpmpd.h>
423-
424-
dsi@ae94000 {
425-
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
426-
reg = <0x0ae94000 0x400>;
427-
reg-names = "dsi_ctrl";
428-
429-
#address-cells = <1>;
430-
#size-cells = <0>;
431-
432-
interrupt-parent = <&mdss>;
433-
interrupts = <4>;
434-
435-
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
436-
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
437-
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
438-
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
439-
<&dispcc DISP_CC_MDSS_AHB_CLK>,
440-
<&dispcc DISP_CC_MDSS_AXI_CLK>;
441-
clock-names = "byte",
442-
"byte_intf",
443-
"pixel",
444-
"core",
445-
"iface",
446-
"bus";
447-
448-
phys = <&dsi0_phy>;
449-
phy-names = "dsi";
450-
451-
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
452-
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
453-
454-
power-domains = <&rpmhpd SC7180_CX>;
455-
operating-points-v2 = <&dsi_opp_table>;
456-
457-
ports {
458-
#address-cells = <1>;
459-
#size-cells = <0>;
460-
461-
port@0 {
462-
reg = <0>;
463-
dsi0_in: endpoint {
464-
remote-endpoint = <&dpu_intf1_out>;
465-
};
466-
};
467-
468-
port@1 {
469-
reg = <1>;
470-
dsi0_out: endpoint {
471-
remote-endpoint = <&sn65dsi86_in>;
472-
data-lanes = <0 1 2 3>;
473-
qcom,te-source = "mdp_vsync_e";
474-
};
475-
};
476-
};
477-
};
419+
#include <dt-bindings/interrupt-controller/arm-gic.h>
420+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
421+
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
422+
#include <dt-bindings/power/qcom-rpmpd.h>
423+
424+
dsi@ae94000 {
425+
compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
426+
reg = <0x0ae94000 0x400>;
427+
reg-names = "dsi_ctrl";
428+
429+
#address-cells = <1>;
430+
#size-cells = <0>;
431+
432+
interrupt-parent = <&mdss>;
433+
interrupts = <4>;
434+
435+
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
436+
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
437+
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
438+
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
439+
<&dispcc DISP_CC_MDSS_AHB_CLK>,
440+
<&dispcc DISP_CC_MDSS_AXI_CLK>;
441+
clock-names = "byte",
442+
"byte_intf",
443+
"pixel",
444+
"core",
445+
"iface",
446+
"bus";
447+
448+
phys = <&dsi0_phy>;
449+
phy-names = "dsi";
450+
451+
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
452+
assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
453+
454+
power-domains = <&rpmhpd SC7180_CX>;
455+
operating-points-v2 = <&dsi_opp_table>;
456+
457+
ports {
458+
#address-cells = <1>;
459+
#size-cells = <0>;
460+
461+
port@0 {
462+
reg = <0>;
463+
endpoint {
464+
remote-endpoint = <&dpu_intf1_out>;
465+
};
466+
};
467+
468+
port@1 {
469+
reg = <1>;
470+
endpoint {
471+
remote-endpoint = <&sn65dsi86_in>;
472+
data-lanes = <0 1 2 3>;
473+
qcom,te-source = "mdp_vsync_e";
474+
};
475+
};
476+
};
477+
};
478478
...

‎Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -74,28 +74,28 @@ unevaluatedProperties: false
7474

7575
examples:
7676
- |
77-
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
78-
#include <dt-bindings/clock/qcom,rpmh.h>
79-
80-
dsi-phy@ae94400 {
81-
compatible = "qcom,dsi-phy-10nm";
82-
reg = <0x0ae94400 0x200>,
83-
<0x0ae94600 0x280>,
84-
<0x0ae94a00 0x1e0>;
85-
reg-names = "dsi_phy",
86-
"dsi_phy_lane",
87-
"dsi_pll";
88-
89-
#clock-cells = <1>;
90-
#phy-cells = <0>;
91-
92-
vdds-supply = <&vdda_mipi_dsi0_pll>;
93-
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
94-
<&rpmhcc RPMH_CXO_CLK>;
95-
clock-names = "iface", "ref";
96-
97-
qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98-
qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
99-
qcom,phy-drive-ldo-level = <400>;
100-
};
77+
#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
78+
#include <dt-bindings/clock/qcom,rpmh.h>
79+
80+
dsi-phy@ae94400 {
81+
compatible = "qcom,dsi-phy-10nm";
82+
reg = <0x0ae94400 0x200>,
83+
<0x0ae94600 0x280>,
84+
<0x0ae94a00 0x1e0>;
85+
reg-names = "dsi_phy",
86+
"dsi_phy_lane",
87+
"dsi_pll";
88+
89+
#clock-cells = <1>;
90+
#phy-cells = <0>;
91+
92+
vdds-supply = <&vdda_mipi_dsi0_pll>;
93+
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
94+
<&rpmhcc RPMH_CXO_CLK>;
95+
clock-names = "iface", "ref";
96+
97+
qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98+
qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
99+
qcom,phy-drive-ldo-level = <400>;
100+
};
101101
...

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