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AngeloGioacchino Del RegnoUlf Hansson
AngeloGioacchino Del Regno
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Ulf Hansson
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pmdomain: mediatek: Add support for MT8196 SCPSYS power domains
Add a new SPM bus protection block and add support for both the direct control and HW Voter control SCPSYS power domains found in the MT8196 and MT6991 SoCs. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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‎drivers/pmdomain/mediatek/mt8196-pm-domains.h‎

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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2025 Collabora Ltd
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef __SOC_MEDIATEK_MT8196_PM_DOMAINS_H
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#define __SOC_MEDIATEK_MT8196_PM_DOMAINS_H
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#include "mtk-pm-domains.h"
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#include <dt-bindings/power/mediatek,mt8196-power.h>
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/*
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* MT8196 and MT6991 power domain support
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*/
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/* INFRA TOP_AXI registers */
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#define MT8196_TOP_AXI_PROT_EN_SET 0x4
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#define MT8196_TOP_AXI_PROT_EN_CLR 0x8
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#define MT8196_TOP_AXI_PROT_EN_STA 0xc
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#define MT8196_TOP_AXI_PROT_EN_SLEEP0_MD BIT(29)
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#define MT8196_TOP_AXI_PROT_EN_1_SET 0x24
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#define MT8196_TOP_AXI_PROT_EN_1_CLR 0x28
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#define MT8196_TOP_AXI_PROT_EN_1_STA 0x2c
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#define MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD BIT(0)
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/* SPM BUS_PROTECT registers */
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#define MT8196_SPM_BUS_PROTECT_CON_SET 0xdc
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#define MT8196_SPM_BUS_PROTECT_CON_CLR 0xe0
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#define MT8196_SPM_BUS_PROTECT_RDY 0x208
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#define MT8196_SPM_PROT_EN_BUS_CONN BIT(1)
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#define MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0 BIT(6)
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#define MT8196_SPM_PROT_EN_BUS_SSUSB_P0 BIT(7)
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#define MT8196_SPM_PROT_EN_BUS_SSUSB_P1 BIT(8)
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#define MT8196_SPM_PROT_EN_BUS_SSUSB_P23 BIT(9)
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#define MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2 BIT(10)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0 BIT(13)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1 BIT(14)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2 BIT(15)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0 BIT(16)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1 BIT(17)
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#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2 BIT(18)
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#define MT8196_SPM_PROT_EN_BUS_AUDIO BIT(19)
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#define MT8196_SPM_PROT_EN_BUS_ADSP_TOP BIT(21)
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#define MT8196_SPM_PROT_EN_BUS_ADSP_INFRA BIT(22)
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#define MT8196_SPM_PROT_EN_BUS_ADSP_AO BIT(23)
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#define MT8196_SPM_PROT_EN_BUS_MM_PROC BIT(24)
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/* PWR_CON registers */
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#define MT8196_PWR_ACK BIT(30)
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#define MT8196_PWR_ACK_2ND BIT(31)
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static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8196[] = {
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BUS_PROT_BLOCK_INFRA, BUS_PROT_BLOCK_SPM
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};
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static const struct scpsys_domain_data scpsys_domain_data_mt8196[] = {
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[MT8196_POWER_DOMAIN_MD] = {
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.name = "md",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe00,
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.pwr_sta_offs = 0xe00,
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.pwr_sta2nd_offs = 0xe00,
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.ext_buck_iso_offs = 0xefc,
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.ext_buck_iso_mask = GENMASK(1, 0),
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.bp_cfg = {
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BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_SLEEP0_MD,
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MT8196_TOP_AXI_PROT_EN_SET,
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MT8196_TOP_AXI_PROT_EN_CLR,
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MT8196_TOP_AXI_PROT_EN_STA),
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BUS_PROT_WR_IGN(INFRA, MT8196_TOP_AXI_PROT_EN_1_SLEEP1_MD,
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MT8196_TOP_AXI_PROT_EN_1_SET,
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MT8196_TOP_AXI_PROT_EN_1_CLR,
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MT8196_TOP_AXI_PROT_EN_1_STA),
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},
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.caps = MTK_SCPD_MODEM_PWRSEQ | MTK_SCPD_EXT_BUCK_ISO |
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MTK_SCPD_SKIP_RESET_B | MTK_SCPD_KEEP_DEFAULT_OFF,
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},
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[MT8196_POWER_DOMAIN_CONN] = {
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.name = "conn",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe04,
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.pwr_sta_offs = 0xe04,
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.pwr_sta2nd_offs = 0xe04,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_CONN,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0] = {
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.name = "ssusb-dp-phy-p0",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe18,
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.pwr_sta_offs = 0xe18,
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.pwr_sta2nd_offs = 0xe18,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_SSUSB_P0] = {
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.name = "ssusb-p0",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe1c,
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.pwr_sta_offs = 0xe1c,
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.pwr_sta2nd_offs = 0xe1c,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P0,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_SSUSB_P1] = {
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.name = "ssusb-p1",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe20,
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.pwr_sta_offs = 0xe20,
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.pwr_sta2nd_offs = 0xe20,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P1,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_SSUSB_P23] = {
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.name = "ssusb-p23",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe24,
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.pwr_sta_offs = 0xe24,
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.pwr_sta2nd_offs = 0xe24,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_P23,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_SSUSB_PHY_P2] = {
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.name = "ssusb-phy-p2",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe28,
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.pwr_sta_offs = 0xe28,
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.pwr_sta2nd_offs = 0xe28,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_KEEP_DEFAULT_OFF,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_PEXTP_MAC0] = {
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.name = "pextp-mac0",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe34,
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.pwr_sta_offs = 0xe34,
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.pwr_sta2nd_offs = 0xe34,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_PEXTP_MAC1] = {
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.name = "pextp-mac1",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe38,
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.pwr_sta_offs = 0xe38,
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.pwr_sta2nd_offs = 0xe38,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_PEXTP_MAC2] = {
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.name = "pextp-mac2",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe3c,
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.pwr_sta_offs = 0xe3c,
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.pwr_sta2nd_offs = 0xe3c,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_PEXTP_PHY0] = {
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.name = "pextp-phy0",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe40,
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.pwr_sta_offs = 0xe40,
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.pwr_sta2nd_offs = 0xe40,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_PEXTP_PHY1] = {
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.name = "pextp-phy1",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe44,
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.pwr_sta_offs = 0xe44,
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.pwr_sta2nd_offs = 0xe44,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_PEXTP_PHY2] = {
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.name = "pextp-phy2",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe48,
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.pwr_sta_offs = 0xe48,
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.pwr_sta2nd_offs = 0xe48,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_PCIE_PHY,
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},
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[MT8196_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe4c,
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.pwr_sta_offs = 0xe4c,
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.pwr_sta2nd_offs = 0xe4c,
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.sram_pdn_bits = BIT(8),
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.sram_pdn_ack_bits = BIT(12),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_AUDIO,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT] = {
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.name = "adsp-top-dormant",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe54,
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.pwr_sta_offs = 0xe54,
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.pwr_sta2nd_offs = 0xe54,
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/* Note: This is not managing powerdown (pdn), but sleep instead (slp) */
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.sram_pdn_bits = BIT(9),
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.sram_pdn_ack_bits = BIT(13),
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_TOP,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_PDN_INVERTED,
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},
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[MT8196_POWER_DOMAIN_ADSP_INFRA] = {
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.name = "adsp-infra",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe58,
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.pwr_sta_offs = 0xe58,
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.pwr_sta2nd_offs = 0xe58,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_INFRA,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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[MT8196_POWER_DOMAIN_ADSP_AO] = {
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.name = "adsp-ao",
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.sta_mask = MT8196_PWR_ACK,
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.sta2nd_mask = MT8196_PWR_ACK_2ND,
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.ctl_offs = 0xe5c,
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.pwr_sta_offs = 0xe5c,
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.pwr_sta2nd_offs = 0xe5c,
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.bp_cfg = {
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BUS_PROT_WR_IGN(SPM, MT8196_SPM_PROT_EN_BUS_ADSP_AO,
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MT8196_SPM_BUS_PROTECT_CON_SET,
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MT8196_SPM_BUS_PROTECT_CON_CLR,
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MT8196_SPM_BUS_PROTECT_RDY),
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},
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.caps = MTK_SCPD_ALWAYS_ON,
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.rtff_type = SCPSYS_RTFF_TYPE_GENERIC,
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},
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};
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static const struct scpsys_hwv_domain_data scpsys_hwv_domain_data_mt8196[] = {
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[MT8196_POWER_DOMAIN_MM_PROC_DORMANT] = {
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.name = "mm-proc-dormant",
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.set = 0x0218,
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.clr = 0x021c,
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.done = 0x141c,
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.en = 0x1410,
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.set_sta = 0x146c,
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.clr_sta = 0x1470,
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.setclr_bit = 0,
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.caps = MTK_SCPD_ALWAYS_ON,
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},
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[MT8196_POWER_DOMAIN_SSR] = {
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.name = "ssrsys",
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.set = 0x0218,
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.clr = 0x021c,
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.done = 0x141c,
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.en = 0x1410,
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.set_sta = 0x146c,
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.clr_sta = 0x1470,
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.setclr_bit = 1,
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},
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};
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static const struct scpsys_soc_data mt8196_scpsys_data = {
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.domains_data = scpsys_domain_data_mt8196,
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.num_domains = ARRAY_SIZE(scpsys_domain_data_mt8196),
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.bus_prot_blocks = scpsys_bus_prot_blocks_mt8196,
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.num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8196),
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.type = SCPSYS_MTCMOS_TYPE_DIRECT_CTL,
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};
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static const struct scpsys_soc_data mt8196_scpsys_hwv_data = {
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.hwv_domains_data = scpsys_hwv_domain_data_mt8196,
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.num_hwv_domains = ARRAY_SIZE(scpsys_hwv_domain_data_mt8196),
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.type = SCPSYS_MTCMOS_TYPE_HW_VOTER,
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};
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#endif /* __SOC_MEDIATEK_MT8196_PM_DOMAINS_H */

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