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clk: tegra: dfll: Add CVB tables for Tegra114
Extend the Tegra124 DFLL driver to include configuration settings required for Tegra114 compatibility. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> [treding@nvidia.com: Use TEGRA210 instead of T210] Signed-off-by: Thierry Reding <treding@nvidia.com>
1 parent 8e7bd52 commit 5aba939

2 files changed

Lines changed: 132 additions & 28 deletions

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‎drivers/clk/tegra/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ config CLK_TEGRA_BPMP
44
depends on TEGRA_BPMP
55

66
config TEGRA_CLK_DFLL
7-
depends on ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
7+
depends on ARCH_TEGRA_114_SOC || ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC
88
select PM_OPP
99
def_bool y
1010

‎drivers/clk/tegra/clk-tegra124-dfll-fcpu.c‎

Lines changed: 131 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,99 @@ struct dfll_fcpu_data {
2828
unsigned int cpu_cvb_tables_size;
2929
};
3030

31+
/* Maximum CPU frequency, indexed by CPU speedo id */
32+
static const unsigned long tegra114_cpu_max_freq_table[] = {
33+
[0] = 2040000000UL,
34+
[1] = 1810500000UL,
35+
[2] = 1912500000UL,
36+
[3] = 1810500000UL,
37+
};
38+
39+
#define T114_CPU_CVB_TABLE \
40+
.min_millivolts = 1000, \
41+
.max_millivolts = 1320, \
42+
.speedo_scale = 100, \
43+
.voltage_scale = 1000, \
44+
.entries = { \
45+
{ 306000000UL, { 2190643, -141851, 3576 } }, \
46+
{ 408000000UL, { 2250968, -144331, 3576 } }, \
47+
{ 510000000UL, { 2313333, -146811, 3576 } }, \
48+
{ 612000000UL, { 2377738, -149291, 3576 } }, \
49+
{ 714000000UL, { 2444183, -151771, 3576 } }, \
50+
{ 816000000UL, { 2512669, -154251, 3576 } }, \
51+
{ 918000000UL, { 2583194, -156731, 3576 } }, \
52+
{ 1020000000UL, { 2655759, -159211, 3576 } }, \
53+
{ 1122000000UL, { 2730365, -161691, 3576 } }, \
54+
{ 1224000000UL, { 2807010, -164171, 3576 } }, \
55+
{ 1326000000UL, { 2885696, -166651, 3576 } }, \
56+
{ 1428000000UL, { 2966422, -169131, 3576 } }, \
57+
{ 1530000000UL, { 3049183, -171601, 3576 } }, \
58+
{ 1606500000UL, { 3112179, -173451, 3576 } }, \
59+
{ 1708500000UL, { 3198504, -175931, 3576 } }, \
60+
{ 1810500000UL, { 3304747, -179126, 3576 } }, \
61+
{ 1912500000UL, { 3395401, -181606, 3576 } }, \
62+
{ 0UL, { 0, 0, 0 } }, \
63+
}, \
64+
.cpu_dfll_data = { \
65+
.tune0_low = 0x00b0039d, \
66+
.tune0_high = 0x00b0009d, \
67+
.tune1 = 0x0000001f, \
68+
.tune_high_min_millivolts = 1050, \
69+
}
70+
71+
static const struct cvb_table tegra114_cpu_cvb_tables[] = {
72+
{
73+
.speedo_id = 0,
74+
.process_id = -1,
75+
.min_millivolts = 1000,
76+
.max_millivolts = 1250,
77+
.speedo_scale = 100,
78+
.voltage_scale = 100,
79+
.entries = {
80+
{ 306000000UL, { 107330, -1569, 0 } },
81+
{ 408000000UL, { 111250, -1666, 0 } },
82+
{ 510000000UL, { 110000, -1460, 0 } },
83+
{ 612000000UL, { 117290, -1745, 0 } },
84+
{ 714000000UL, { 122700, -1910, 0 } },
85+
{ 816000000UL, { 125620, -1945, 0 } },
86+
{ 918000000UL, { 130560, -2076, 0 } },
87+
{ 1020000000UL, { 137280, -2303, 0 } },
88+
{ 1122000000UL, { 146440, -2660, 0 } },
89+
{ 1224000000UL, { 152190, -2825, 0 } },
90+
{ 1326000000UL, { 157520, -2953, 0 } },
91+
{ 1428000000UL, { 166100, -3261, 0 } },
92+
{ 1530000000UL, { 176410, -3647, 0 } },
93+
{ 1632000000UL, { 189620, -4186, 0 } },
94+
{ 1734000000UL, { 203190, -4725, 0 } },
95+
{ 1836000000UL, { 222670, -5573, 0 } },
96+
{ 1938000000UL, { 256210, -7165, 0 } },
97+
{ 2040000000UL, { 250050, -6544, 0 } },
98+
{ 0UL, { 0, 0, 0 } },
99+
},
100+
.cpu_dfll_data = {
101+
.tune0_low = 0x00b0019d,
102+
.tune0_high = 0x00b0019d,
103+
.tune1 = 0x0000001f,
104+
.tune_high_min_millivolts = 1000,
105+
}
106+
},
107+
{
108+
.speedo_id = 1,
109+
.process_id = -1,
110+
T114_CPU_CVB_TABLE
111+
},
112+
{
113+
.speedo_id = 2,
114+
.process_id = -1,
115+
T114_CPU_CVB_TABLE
116+
},
117+
{
118+
.speedo_id = 3,
119+
.process_id = -1,
120+
T114_CPU_CVB_TABLE
121+
},
122+
};
123+
31124
/* Maximum CPU frequency, indexed by CPU speedo id */
32125
static const unsigned long tegra124_cpu_max_freq_table[] = {
33126
[0] = 2014500000UL,
@@ -93,7 +186,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
93186
[10] = 1504500000UL,
94187
};
95188

96-
#define CPU_CVB_TABLE \
189+
#define TEGRA210_CPU_CVB_TABLE \
97190
.speedo_scale = 100, \
98191
.voltage_scale = 1000, \
99192
.entries = { \
@@ -120,7 +213,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
120213
{ 0UL, { 0, 0, 0 } }, \
121214
}
122215

123-
#define CPU_CVB_TABLE_XA \
216+
#define TEGRA210_CPU_CVB_TABLE_XA \
124217
.speedo_scale = 100, \
125218
.voltage_scale = 1000, \
126219
.entries = { \
@@ -143,7 +236,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
143236
{ 0UL, { 0, 0, 0 } }, \
144237
}
145238

146-
#define CPU_CVB_TABLE_EUCM1 \
239+
#define TEGRA210_CPU_CVB_TABLE_EUCM1 \
147240
.speedo_scale = 100, \
148241
.voltage_scale = 1000, \
149242
.entries = { \
@@ -166,7 +259,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
166259
{ 0UL, { 0, 0, 0 } }, \
167260
}
168261

169-
#define CPU_CVB_TABLE_EUCM2 \
262+
#define TEGRA210_CPU_CVB_TABLE_EUCM2 \
170263
.speedo_scale = 100, \
171264
.voltage_scale = 1000, \
172265
.entries = { \
@@ -188,7 +281,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
188281
{ 0UL, { 0, 0, 0 } }, \
189282
}
190283

191-
#define CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
284+
#define TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL \
192285
.speedo_scale = 100, \
193286
.voltage_scale = 1000, \
194287
.entries = { \
@@ -209,7 +302,7 @@ static const unsigned long tegra210_cpu_max_freq_table[] = {
209302
{ 0UL, { 0, 0, 0 } }, \
210303
}
211304

212-
#define CPU_CVB_TABLE_ODN \
305+
#define TEGRA210_CPU_CVB_TABLE_ODN \
213306
.speedo_scale = 100, \
214307
.voltage_scale = 1000, \
215308
.entries = { \
@@ -238,7 +331,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
238331
.process_id = 0,
239332
.min_millivolts = 840,
240333
.max_millivolts = 1120,
241-
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
334+
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
242335
.cpu_dfll_data = {
243336
.tune0_low = 0xffead0ff,
244337
.tune0_high = 0xffead0ff,
@@ -251,7 +344,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
251344
.process_id = 1,
252345
.min_millivolts = 840,
253346
.max_millivolts = 1120,
254-
CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
347+
TEGRA210_CPU_CVB_TABLE_EUCM2_JOINT_RAIL,
255348
.cpu_dfll_data = {
256349
.tune0_low = 0xffead0ff,
257350
.tune0_high = 0xffead0ff,
@@ -264,7 +357,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
264357
.process_id = 0,
265358
.min_millivolts = 900,
266359
.max_millivolts = 1162,
267-
CPU_CVB_TABLE_EUCM2,
360+
TEGRA210_CPU_CVB_TABLE_EUCM2,
268361
.cpu_dfll_data = {
269362
.tune0_low = 0xffead0ff,
270363
.tune0_high = 0xffead0ff,
@@ -276,7 +369,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
276369
.process_id = 1,
277370
.min_millivolts = 900,
278371
.max_millivolts = 1162,
279-
CPU_CVB_TABLE_EUCM2,
372+
TEGRA210_CPU_CVB_TABLE_EUCM2,
280373
.cpu_dfll_data = {
281374
.tune0_low = 0xffead0ff,
282375
.tune0_high = 0xffead0ff,
@@ -288,7 +381,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
288381
.process_id = 0,
289382
.min_millivolts = 900,
290383
.max_millivolts = 1195,
291-
CPU_CVB_TABLE_EUCM2,
384+
TEGRA210_CPU_CVB_TABLE_EUCM2,
292385
.cpu_dfll_data = {
293386
.tune0_low = 0xffead0ff,
294387
.tune0_high = 0xffead0ff,
@@ -300,7 +393,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
300393
.process_id = 1,
301394
.min_millivolts = 900,
302395
.max_millivolts = 1195,
303-
CPU_CVB_TABLE_EUCM2,
396+
TEGRA210_CPU_CVB_TABLE_EUCM2,
304397
.cpu_dfll_data = {
305398
.tune0_low = 0xffead0ff,
306399
.tune0_high = 0xffead0ff,
@@ -312,7 +405,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
312405
.process_id = 0,
313406
.min_millivolts = 841,
314407
.max_millivolts = 1227,
315-
CPU_CVB_TABLE_EUCM1,
408+
TEGRA210_CPU_CVB_TABLE_EUCM1,
316409
.cpu_dfll_data = {
317410
.tune0_low = 0xffead0ff,
318411
.tune0_high = 0xffead0ff,
@@ -325,7 +418,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
325418
.process_id = 1,
326419
.min_millivolts = 841,
327420
.max_millivolts = 1227,
328-
CPU_CVB_TABLE_EUCM1,
421+
TEGRA210_CPU_CVB_TABLE_EUCM1,
329422
.cpu_dfll_data = {
330423
.tune0_low = 0xffead0ff,
331424
.tune0_high = 0xffead0ff,
@@ -338,7 +431,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
338431
.process_id = 0,
339432
.min_millivolts = 870,
340433
.max_millivolts = 1150,
341-
CPU_CVB_TABLE,
434+
TEGRA210_CPU_CVB_TABLE,
342435
.cpu_dfll_data = {
343436
.tune0_low = 0xffead0ff,
344437
.tune1 = 0x20091d9,
@@ -349,7 +442,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
349442
.process_id = 1,
350443
.min_millivolts = 870,
351444
.max_millivolts = 1150,
352-
CPU_CVB_TABLE,
445+
TEGRA210_CPU_CVB_TABLE,
353446
.cpu_dfll_data = {
354447
.tune0_low = 0xffead0ff,
355448
.tune1 = 0x25501d0,
@@ -360,7 +453,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
360453
.process_id = 0,
361454
.min_millivolts = 818,
362455
.max_millivolts = 1227,
363-
CPU_CVB_TABLE,
456+
TEGRA210_CPU_CVB_TABLE,
364457
.cpu_dfll_data = {
365458
.tune0_low = 0xffead0ff,
366459
.tune0_high = 0xffead0ff,
@@ -373,7 +466,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
373466
.process_id = 1,
374467
.min_millivolts = 818,
375468
.max_millivolts = 1227,
376-
CPU_CVB_TABLE,
469+
TEGRA210_CPU_CVB_TABLE,
377470
.cpu_dfll_data = {
378471
.tune0_low = 0xffead0ff,
379472
.tune0_high = 0xffead0ff,
@@ -386,7 +479,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
386479
.process_id = -1,
387480
.min_millivolts = 918,
388481
.max_millivolts = 1113,
389-
CPU_CVB_TABLE_XA,
482+
TEGRA210_CPU_CVB_TABLE_XA,
390483
.cpu_dfll_data = {
391484
.tune0_low = 0xffead0ff,
392485
.tune1 = 0x17711BD,
@@ -397,7 +490,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
397490
.process_id = 0,
398491
.min_millivolts = 825,
399492
.max_millivolts = 1227,
400-
CPU_CVB_TABLE_ODN,
493+
TEGRA210_CPU_CVB_TABLE_ODN,
401494
.cpu_dfll_data = {
402495
.tune0_low = 0xffead0ff,
403496
.tune0_high = 0xffead0ff,
@@ -410,7 +503,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
410503
.process_id = 1,
411504
.min_millivolts = 825,
412505
.max_millivolts = 1227,
413-
CPU_CVB_TABLE_ODN,
506+
TEGRA210_CPU_CVB_TABLE_ODN,
414507
.cpu_dfll_data = {
415508
.tune0_low = 0xffead0ff,
416509
.tune0_high = 0xffead0ff,
@@ -423,7 +516,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
423516
.process_id = 0,
424517
.min_millivolts = 870,
425518
.max_millivolts = 1227,
426-
CPU_CVB_TABLE,
519+
TEGRA210_CPU_CVB_TABLE,
427520
.cpu_dfll_data = {
428521
.tune0_low = 0xffead0ff,
429522
.tune1 = 0x20091d9,
@@ -434,7 +527,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
434527
.process_id = 1,
435528
.min_millivolts = 870,
436529
.max_millivolts = 1227,
437-
CPU_CVB_TABLE,
530+
TEGRA210_CPU_CVB_TABLE,
438531
.cpu_dfll_data = {
439532
.tune0_low = 0xffead0ff,
440533
.tune1 = 0x25501d0,
@@ -445,7 +538,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
445538
.process_id = 0,
446539
.min_millivolts = 837,
447540
.max_millivolts = 1227,
448-
CPU_CVB_TABLE,
541+
TEGRA210_CPU_CVB_TABLE,
449542
.cpu_dfll_data = {
450543
.tune0_low = 0xffead0ff,
451544
.tune0_high = 0xffead0ff,
@@ -458,7 +551,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
458551
.process_id = 1,
459552
.min_millivolts = 837,
460553
.max_millivolts = 1227,
461-
CPU_CVB_TABLE,
554+
TEGRA210_CPU_CVB_TABLE,
462555
.cpu_dfll_data = {
463556
.tune0_low = 0xffead0ff,
464557
.tune0_high = 0xffead0ff,
@@ -471,7 +564,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
471564
.process_id = 0,
472565
.min_millivolts = 850,
473566
.max_millivolts = 1170,
474-
CPU_CVB_TABLE,
567+
TEGRA210_CPU_CVB_TABLE,
475568
.cpu_dfll_data = {
476569
.tune0_low = 0xffead0ff,
477570
.tune0_high = 0xffead0ff,
@@ -484,7 +577,7 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
484577
.process_id = 1,
485578
.min_millivolts = 850,
486579
.max_millivolts = 1170,
487-
CPU_CVB_TABLE,
580+
TEGRA210_CPU_CVB_TABLE,
488581
.cpu_dfll_data = {
489582
.tune0_low = 0xffead0ff,
490583
.tune0_high = 0xffead0ff,
@@ -494,6 +587,13 @@ static struct cvb_table tegra210_cpu_cvb_tables[] = {
494587
},
495588
};
496589

590+
static const struct dfll_fcpu_data tegra114_dfll_fcpu_data = {
591+
.cpu_max_freq_table = tegra114_cpu_max_freq_table,
592+
.cpu_max_freq_table_size = ARRAY_SIZE(tegra114_cpu_max_freq_table),
593+
.cpu_cvb_tables = tegra114_cpu_cvb_tables,
594+
.cpu_cvb_tables_size = ARRAY_SIZE(tegra114_cpu_cvb_tables)
595+
};
596+
497597
static const struct dfll_fcpu_data tegra124_dfll_fcpu_data = {
498598
.cpu_max_freq_table = tegra124_cpu_max_freq_table,
499599
.cpu_max_freq_table_size = ARRAY_SIZE(tegra124_cpu_max_freq_table),
@@ -509,6 +609,10 @@ static const struct dfll_fcpu_data tegra210_dfll_fcpu_data = {
509609
};
510610

511611
static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
612+
{
613+
.compatible = "nvidia,tegra114-dfll",
614+
.data = &tegra114_dfll_fcpu_data,
615+
},
512616
{
513617
.compatible = "nvidia,tegra124-dfll",
514618
.data = &tegra124_dfll_fcpu_data,

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