dmaengine: xilinx: xdma: Fix wrong offsets in the buffers addresses in dma descriptor

miquelraynal · vinodkoul · commit 5b9706bfc094 · 2024-04-07T17:08:45.000+05:30
The addition of interleaved transfers slightly changed the way addresses inside DMA descriptors are derived, breaking cyclic transfers. Fixes: 3e184e6 ("dmaengine: xilinx: xdma: Prepare the introduction of interleaved DMA transfers") Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com> Link: https://lore.kernel.org/r/20240327-digigram-xdma-fixes-v1-1-45f4a52c0283@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c
@@ -704,7 +704,7 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address,
 	desc_num = 0;
 	for (i = 0; i < periods; i++) {
 		desc_num += xdma_fill_descs(sw_desc, *src, *dst, period_size, desc_num);
-		addr += i * period_size;
+		addr += period_size;
 	}
 
 	tx_desc = vchan_tx_prep(&xdma_chan->vchan, &sw_desc->vdesc, flags);

Original file line number	Diff line number	Diff line change
`@@ -704,7 +704,7 @@ xdma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t address,`
`704`	`704`	`desc_num = 0;`
`705`	`705`	`for (i = 0; i < periods; i++) {`
`706`	`706`	`desc_num += xdma_fill_descs(sw_desc, src, dst, period_size, desc_num);`
`707`		`- addr += i * period_size;`
	`707`	`+ addr += period_size;`
`708`	`708`	`}`
`709`	`709`
`710`	`710`	`tx_desc = vchan_tx_prep(&xdma_chan->vchan, &sw_desc->vdesc, flags);`