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captain5050
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perf vendor events intel: Update lunarlake events from 1.18 to 1.19
The updated events were published in: intel/perfmon@09a0c74 Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
1 parent cf99cdf commit 60688cf

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‎tools/perf/pmu-events/arch/x86/lunarlake/cache.json‎

Lines changed: 10 additions & 10 deletions
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@@ -243,7 +243,7 @@
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
246+
"BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x28",
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"EventName": "L2_PREFETCHES_THROTTLED.XQ_THRESH",
@@ -464,7 +464,7 @@
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
467+
"BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESHOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x29",
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"EventName": "LLC_PREFETCHES_THROTTLED.XQ_THRESH",
@@ -1089,7 +1089,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
@@ -1101,7 +1101,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
@@ -1113,7 +1113,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
@@ -1125,7 +1125,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
@@ -1137,7 +1137,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
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"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
@@ -1149,7 +1149,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
1152-
"Counter": "0,1,2,3,4,5,6,7",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
@@ -1161,7 +1161,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
1164-
"Counter": "0,1,2,3,4,5,6,7",
1164+
"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
@@ -1173,7 +1173,7 @@
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
1176-
"Counter": "0,1,2,3,4,5,6,7",
1176+
"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

‎tools/perf/pmu-events/arch/x86/lunarlake/other.json‎

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@@ -178,6 +178,7 @@
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"EventCode": "0xf4",
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"EventName": "XQ_PROMOTION.ALL",
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"SampleAfterValue": "1000003",
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"UMask": "0x7",
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"Unit": "cpu_atom"
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},
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{

‎tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json‎

Lines changed: 23 additions & 3 deletions
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@@ -21,17 +21,19 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of active floating point and integer dividers per cycle.",
24+
"BriefDescription": "This event is deprecated.",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xcd",
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"EventName": "ARITH.DIV_OCCUPANCY",
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"SampleAfterValue": "1000003",
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"UMask": "0x3",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of floating point and integer divider uops executed per cycle.",
34+
"BriefDescription": "This event is deprecated.",
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"Counter": "0,1,2,3,4,5,6,7",
36+
"Deprecated": "1",
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"EventCode": "0xcd",
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"EventName": "ARITH.DIV_UOPS",
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"SampleAfterValue": "1000003",
@@ -1023,6 +1025,15 @@
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"UMask": "0x10",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of uops executed on secondary integer ports 0,1,2,3.",
1030+
"Counter": "0,1,2,3,4,5,6,7",
1031+
"EventCode": "0xb3",
1032+
"EventName": "INT_UOPS_EXECUTED.2ND",
1033+
"SampleAfterValue": "1000003",
1034+
"UMask": "0x80",
1035+
"Unit": "cpu_atom"
1036+
},
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{
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"BriefDescription": "Counts the number of uops executed on all Integer ports.",
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"Counter": "0,1,2,3,4,5,6,7",
@@ -1205,7 +1216,7 @@
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"EventCode": "0x03",
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"EventName": "LD_BLOCKS.ALL",
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"SampleAfterValue": "1000003",
1208-
"UMask": "0x10",
1219+
"UMask": "0x1f",
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"Unit": "cpu_atom"
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},
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{
@@ -1613,6 +1624,15 @@
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"UMask": "0x8",
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"Unit": "cpu_atom"
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},
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{
1628+
"BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
1629+
"Counter": "0,1,2,3,4,5,6,7",
1630+
"EventCode": "0x75",
1631+
"EventName": "SERIALIZATION.IQ_JEU_SCB",
1632+
"SampleAfterValue": "1000003",
1633+
"UMask": "0x1",
1634+
"Unit": "cpu_atom"
1635+
},
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{
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"BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
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"Counter": "0,1,2,3,4,5,6,7",

‎tools/perf/pmu-events/arch/x86/mapfile.csv‎

Lines changed: 1 addition & 1 deletion
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@@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
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GenuineIntel-6-3E,v24,ivytown,core
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GenuineIntel-6-2D,v24,jaketown,core
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GenuineIntel-6-(57|85),v16,knightslanding,core
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GenuineIntel-6-BD,v1.18,lunarlake,core
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GenuineIntel-6-BD,v1.19,lunarlake,core
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GenuineIntel-6-(AA|AC|B5),v1.17,meteorlake,core
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GenuineIntel-6-1[AEF],v4,nehalemep,core
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GenuineIntel-6-2E,v4,nehalemex,core

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