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MIPS: dts: loongson: Add LS1B-DEMO board
Add a device tree for LS1B-DEMO board, supporting CPU, clock, INTC, UART, Ethernet, GPIO, USB host, RTC, watchdog, DMA, NAND, and AC97. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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‎MAINTAINERS‎

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@@ -17016,6 +17016,7 @@ M: Keguang Zhang <keguang.zhang@gmail.com>
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L: linux-mips@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/*/loongson,ls1*.yaml
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F: arch/mips/boot/dts/loongson/loongson1*
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F: arch/mips/include/asm/mach-loongson32/
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F: arch/mips/loongson32/
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F: drivers/*/*loongson1*

‎arch/mips/boot/dts/Makefile‎

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@@ -8,6 +8,7 @@ subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
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subdir-$(CONFIG_MACH_INGENIC) += ingenic
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subdir-$(CONFIG_LANTIQ) += lantiq
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subdir-$(CONFIG_MACH_LOONGSON64) += loongson
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subdir-$(CONFIG_MACH_LOONGSON32) += loongson
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subdir-$(CONFIG_SOC_VCOREIII) += mscc
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subdir-$(CONFIG_MIPS_MALTA) += mti
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subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti

‎arch/mips/boot/dts/loongson/Makefile‎

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@@ -5,3 +5,5 @@ dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
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dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
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dtb-$(CONFIG_MACH_LOONGSON32) += ls1b-demo.dtb

‎arch/mips/boot/dts/loongson/loongson1.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
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*/
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/dts-v1/;
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#include <dt-bindings/clock/loongson,ls1x-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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xtal: clock {
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compatible = "fixed-clock";
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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reg = <0>;
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device_type = "cpu";
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clocks = <&clkc LS1X_CLKID_CPU>;
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#clock-cells = <1>;
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};
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};
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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};
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soc: bus@1fd00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1fd00000 0x130000>;
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intc0: interrupt-controller@1040 {
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compatible = "loongson,ls1x-intc";
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reg = <0x1040 0x18>;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>;
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#interrupt-cells = <2>;
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};
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intc1: interrupt-controller@1058 {
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compatible = "loongson,ls1x-intc";
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reg = <0x1058 0x18>;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = <3>;
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#interrupt-cells = <2>;
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};
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intc2: interrupt-controller@1070 {
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compatible = "loongson,ls1x-intc";
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reg = <0x1070 0x18>;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = <4>;
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#interrupt-cells = <2>;
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};
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intc3: interrupt-controller@1088 {
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compatible = "loongson,ls1x-intc";
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reg = <0x1088 0x18>;
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interrupt-controller;
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interrupt-parent = <&cpu_intc>;
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interrupts = <5>;
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#interrupt-cells = <2>;
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};
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gpio0: gpio@10c0 {
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compatible = "loongson,ls1x-gpio";
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reg = <0x10c0 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@10c4 {
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compatible = "loongson,ls1x-gpio";
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reg = <0x10c4 0x4>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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apb: bus@1fe40000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1fe40000 0xc0000>;
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uart0: serial@0 {
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compatible = "ns16550a";
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reg = <0x0 0x8>;
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clocks = <&clkc LS1X_CLKID_APB>;
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interrupt-parent = <&intc0>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart1: serial@4000 {
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compatible = "ns16550a";
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reg = <0x4000 0x8>;
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clocks = <&clkc LS1X_CLKID_APB>;
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interrupt-parent = <&intc0>;
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status = "disabled";
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};
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uart2: serial@8000 {
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compatible = "ns16550a";
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reg = <0x8000 0x8>;
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clocks = <&clkc LS1X_CLKID_APB>;
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interrupt-parent = <&intc0>;
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status = "disabled";
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};
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uart3: serial@c000 {
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compatible = "ns16550a";
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reg = <0xc000 0x8>;
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clocks = <&clkc LS1X_CLKID_APB>;
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interrupt-parent = <&intc0>;
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status = "disabled";
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};
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};
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};

‎arch/mips/boot/dts/loongson/loongson1b.dtsi‎

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
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*/
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/dts-v1/;
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#include "loongson1.dtsi"
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/ {
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-shared;
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opp-44000000 {
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opp-hz = /bits/ 64 <44000000>;
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};
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opp-47142000 {
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opp-hz = /bits/ 64 <47142000>;
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};
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opp-50769000 {
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opp-hz = /bits/ 64 <50769000>;
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};
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opp-55000000 {
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opp-hz = /bits/ 64 <55000000>;
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};
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opp-60000000 {
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opp-hz = /bits/ 64 <60000000>;
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};
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opp-66000000 {
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opp-hz = /bits/ 64 <66000000>;
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};
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opp-73333000 {
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opp-hz = /bits/ 64 <73333000>;
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};
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opp-82500000 {
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opp-hz = /bits/ 64 <82500000>;
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};
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opp-94285000 {
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opp-hz = /bits/ 64 <94285000>;
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};
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opp-110000000 {
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opp-hz = /bits/ 64 <110000000>;
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};
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opp-132000000 {
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opp-hz = /bits/ 64 <132000000>;
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};
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opp-165000000 {
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opp-hz = /bits/ 64 <165000000>;
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};
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opp-220000000 {
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opp-hz = /bits/ 64 <220000000>;
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};
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};
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clkc: clock-controller@1fe78030 {
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compatible = "loongson,ls1b-clk";
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reg = <0x1fe78030 0x8>;
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clocks = <&xtal>;
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#clock-cells = <1>;
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};
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};
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&soc {
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syscon: syscon@420 {
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compatible = "loongson,ls1b-syscon", "syscon";
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reg = <0x420 0x8>;
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};
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dma: dma-controller@1160 {
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compatible = "loongson,ls1b-apbdma";
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reg = <0x1160 0x4>;
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interrupt-parent = <&intc0>;
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interrupts = <13 IRQ_TYPE_EDGE_RISING>,
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<14 IRQ_TYPE_EDGE_RISING>,
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<15 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ch0", "ch1", "ch2";
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#dma-cells = <1>;
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};
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ehci: usb@100000 {
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compatible = "generic-ehci";
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reg = <0x100000 0x100>;
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interrupt-parent = <&intc1>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ohci: usb@108000 {
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compatible = "generic-ohci";
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reg = <0x108000 0x100>;
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interrupt-parent = <&intc1>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gmac0: ethernet@110000 {
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compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
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reg = <0x110000 0x10000>;
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clocks = <&clkc LS1X_CLKID_AHB>;
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clock-names = "stmmaceth";
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interrupt-parent = <&intc1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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loongson,ls1-syscon = <&syscon>;
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snps,pbl = <1>;
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status = "disabled";
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};
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gmac1: ethernet@120000 {
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compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a";
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reg = <0x120000 0x10000>;
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clocks = <&clkc LS1X_CLKID_AHB>;
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clock-names = "stmmaceth";
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interrupt-parent = <&intc1>;
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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loongson,ls1-syscon = <&syscon>;
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snps,pbl = <1>;
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status = "disabled";
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};
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};
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&apb {
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clocksource: timer@1c030 {
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compatible = "loongson,ls1b-pwmtimer";
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reg = <0x1c030 0x10>;
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clocks = <&clkc LS1X_CLKID_APB>;
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interrupt-parent = <&intc0>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog: watchdog@1c060 {
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compatible = "loongson,ls1b-wdt";
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reg = <0x1c060 0xc>;
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clocks = <&clkc LS1X_CLKID_APB>;
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status = "disabled";
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};
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rtc: rtc@24000 {
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compatible = "loongson,ls1b-rtc";
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reg = <0x24000 0x78>;
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interrupt-parent = <&intc0>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ac97: audio-controller@34000 {
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compatible = "loongson,ls1b-ac97";
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reg = <0x34000 0x60>, <0x32420 0x4>, <0x34c4c 0x4>;
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reg-names = "ac97", "audio-tx", "audio-rx";
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dmas = <&dma 1>, <&dma 2>;
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dma-names = "tx", "rx";
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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nand: nand-controller@38000 {
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compatible = "loongson,ls1b-nand-controller";
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reg = <0x38000 0x24>, <0x38040 0x4>;
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reg-names = "nand", "nand-dma";
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dmas = <&dma 0>;
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dma-names = "rxtx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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nand@0 {
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reg = <0>;
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label = "ls1x-nand";
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nand-use-soft-ecc-engine;
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nand-ecc-algo = "hamming";
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};
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};
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};
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&cpu0 {
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operating-points-v2 = <&cpu_opp_table>;
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};
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&gpio0 {
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ngpios = <31>;
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};
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&gpio1 {
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ngpios = <30>;
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};
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&uart1 {
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interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart2 {
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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};
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&uart3 {
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
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};

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