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gcabidduherbertx
gcabiddu
authored and
herbertx
committed
crypto: qat - relocate CSR access code
As the common hw_data files are growing and the adf_hw_csr_ops is going to be extended with new operations, move all logic related to ring CSRs to the newly created adf_gen[2|4]_hw_csr_data.[c|h] files. This does not introduce any functional change. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Xin Zeng <xin.zeng@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
1 parent 867e801 commit 680302d

17 files changed

Lines changed: 397 additions & 362 deletions

‎drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
1010
#include <adf_fw_config.h>
1111
#include <adf_gen4_config.h>
1212
#include <adf_gen4_dc.h>
13+
#include <adf_gen4_hw_csr_data.h>
1314
#include <adf_gen4_hw_data.h>
1415
#include <adf_gen4_pfvf.h>
1516
#include <adf_gen4_pm.h>

‎drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c‎

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
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#include <adf_fw_config.h>
1111
#include <adf_gen4_config.h>
1212
#include <adf_gen4_dc.h>
13+
#include <adf_gen4_hw_csr_data.h>
1314
#include <adf_gen4_hw_data.h>
1415
#include <adf_gen4_pfvf.h>
1516
#include <adf_gen4_pm.h>

‎drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include <adf_common_drv.h>
77
#include <adf_gen2_config.h>
88
#include <adf_gen2_dc.h>
9+
#include <adf_gen2_hw_csr_data.h>
910
#include <adf_gen2_hw_data.h>
1011
#include <adf_gen2_pfvf.h>
1112
#include "adf_c3xxx_hw_data.h"

‎drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
66
#include <adf_gen2_dc.h>
7+
#include <adf_gen2_hw_csr_data.h>
78
#include <adf_gen2_hw_data.h>
89
#include <adf_gen2_pfvf.h>
910
#include <adf_pfvf_vf_msg.h>

‎drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
#include <adf_common_drv.h>
77
#include <adf_gen2_config.h>
88
#include <adf_gen2_dc.h>
9+
#include <adf_gen2_hw_csr_data.h>
910
#include <adf_gen2_hw_data.h>
1011
#include <adf_gen2_pfvf.h>
1112
#include "adf_c62x_hw_data.h"

‎drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include <adf_common_drv.h>
55
#include <adf_gen2_config.h>
66
#include <adf_gen2_dc.h>
7+
#include <adf_gen2_hw_csr_data.h>
78
#include <adf_gen2_hw_data.h>
89
#include <adf_gen2_pfvf.h>
910
#include <adf_pfvf_vf_msg.h>

‎drivers/crypto/intel/qat/qat_common/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,11 @@ intel_qat-objs := adf_cfg.o \
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adf_hw_arbiter.o \
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adf_sysfs.o \
1616
adf_sysfs_ras_counters.o \
17+
adf_gen2_hw_csr_data.o \
1718
adf_gen2_hw_data.o \
1819
adf_gen2_config.o \
1920
adf_gen4_config.o \
21+
adf_gen4_hw_csr_data.o \
2022
adf_gen4_hw_data.o \
2123
adf_gen4_pm.o \
2224
adf_gen2_dc.o \

‎drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.c‎

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
1+
// SPDX-License-Identifier: GPL-2.0-only
2+
/* Copyright(c) 2024 Intel Corporation */
3+
#include <linux/types.h>
4+
#include "adf_gen2_hw_csr_data.h"
5+
6+
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
7+
{
8+
return BUILD_RING_BASE_ADDR(addr, size);
9+
}
10+
11+
static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
12+
{
13+
return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
14+
}
15+
16+
static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
17+
u32 value)
18+
{
19+
WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
20+
}
21+
22+
static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
23+
{
24+
return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
25+
}
26+
27+
static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
28+
u32 value)
29+
{
30+
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
31+
}
32+
33+
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
34+
{
35+
return READ_CSR_E_STAT(csr_base_addr, bank);
36+
}
37+
38+
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
39+
u32 ring, u32 value)
40+
{
41+
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
42+
}
43+
44+
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
45+
dma_addr_t addr)
46+
{
47+
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
48+
}
49+
50+
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
51+
{
52+
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
53+
}
54+
55+
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
56+
{
57+
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
58+
}
59+
60+
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
61+
u32 value)
62+
{
63+
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
64+
}
65+
66+
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
67+
u32 value)
68+
{
69+
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
70+
}
71+
72+
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
73+
u32 value)
74+
{
75+
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
76+
}
77+
78+
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
79+
u32 value)
80+
{
81+
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
82+
}
83+
84+
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
85+
{
86+
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
87+
csr_ops->read_csr_ring_head = read_csr_ring_head;
88+
csr_ops->write_csr_ring_head = write_csr_ring_head;
89+
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
90+
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
91+
csr_ops->read_csr_e_stat = read_csr_e_stat;
92+
csr_ops->write_csr_ring_config = write_csr_ring_config;
93+
csr_ops->write_csr_ring_base = write_csr_ring_base;
94+
csr_ops->write_csr_int_flag = write_csr_int_flag;
95+
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
96+
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
97+
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
98+
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
99+
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
100+
}
101+
EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);

‎drivers/crypto/intel/qat/qat_common/adf_gen2_hw_csr_data.h‎

Lines changed: 86 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,86 @@
1+
/* SPDX-License-Identifier: GPL-2.0-only */
2+
/* Copyright(c) 2024 Intel Corporation */
3+
#ifndef ADF_GEN2_HW_CSR_DATA_H_
4+
#define ADF_GEN2_HW_CSR_DATA_H_
5+
6+
#include <linux/bitops.h>
7+
#include "adf_accel_devices.h"
8+
9+
#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
10+
#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
11+
#define ADF_RING_CSR_RING_CONFIG 0x000
12+
#define ADF_RING_CSR_RING_LBASE 0x040
13+
#define ADF_RING_CSR_RING_UBASE 0x080
14+
#define ADF_RING_CSR_RING_HEAD 0x0C0
15+
#define ADF_RING_CSR_RING_TAIL 0x100
16+
#define ADF_RING_CSR_E_STAT 0x14C
17+
#define ADF_RING_CSR_INT_FLAG 0x170
18+
#define ADF_RING_CSR_INT_SRCSEL 0x174
19+
#define ADF_RING_CSR_INT_SRCSEL_2 0x178
20+
#define ADF_RING_CSR_INT_COL_EN 0x17C
21+
#define ADF_RING_CSR_INT_COL_CTL 0x180
22+
#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
23+
#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
24+
#define ADF_RING_BUNDLE_SIZE 0x1000
25+
#define ADF_ARB_REG_SLOT 0x1000
26+
#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
27+
28+
#define BUILD_RING_BASE_ADDR(addr, size) \
29+
(((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
30+
#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
31+
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
32+
ADF_RING_CSR_RING_HEAD + ((ring) << 2))
33+
#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
34+
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
35+
ADF_RING_CSR_RING_TAIL + ((ring) << 2))
36+
#define READ_CSR_E_STAT(csr_base_addr, bank) \
37+
ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
38+
ADF_RING_CSR_E_STAT)
39+
#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
40+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
41+
ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
42+
#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
43+
do { \
44+
u32 l_base = 0, u_base = 0; \
45+
l_base = (u32)((value) & 0xFFFFFFFF); \
46+
u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
47+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
48+
ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
49+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
50+
ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
51+
} while (0)
52+
53+
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
54+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
55+
ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
56+
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
57+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
58+
ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
59+
#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
60+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
61+
ADF_RING_CSR_INT_FLAG, value)
62+
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
63+
do { \
64+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
65+
ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
66+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
67+
ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
68+
} while (0)
69+
#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
70+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
71+
ADF_RING_CSR_INT_COL_EN, value)
72+
#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
73+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
74+
ADF_RING_CSR_INT_COL_CTL, \
75+
ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
76+
#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
77+
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
78+
ADF_RING_CSR_INT_FLAG_AND_COL, value)
79+
80+
#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
81+
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
82+
(ADF_ARB_REG_SLOT * (index)), value)
83+
84+
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
85+
86+
#endif

‎drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c‎

Lines changed: 0 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -111,103 +111,6 @@ void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev)
111111
}
112112
EXPORT_SYMBOL_GPL(adf_gen2_enable_ints);
113113

114-
static u64 build_csr_ring_base_addr(dma_addr_t addr, u32 size)
115-
{
116-
return BUILD_RING_BASE_ADDR(addr, size);
117-
}
118-
119-
static u32 read_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring)
120-
{
121-
return READ_CSR_RING_HEAD(csr_base_addr, bank, ring);
122-
}
123-
124-
static void write_csr_ring_head(void __iomem *csr_base_addr, u32 bank, u32 ring,
125-
u32 value)
126-
{
127-
WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value);
128-
}
129-
130-
static u32 read_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring)
131-
{
132-
return READ_CSR_RING_TAIL(csr_base_addr, bank, ring);
133-
}
134-
135-
static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
136-
u32 value)
137-
{
138-
WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
139-
}
140-
141-
static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
142-
{
143-
return READ_CSR_E_STAT(csr_base_addr, bank);
144-
}
145-
146-
static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
147-
u32 ring, u32 value)
148-
{
149-
WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
150-
}
151-
152-
static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
153-
dma_addr_t addr)
154-
{
155-
WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
156-
}
157-
158-
static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank, u32 value)
159-
{
160-
WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
161-
}
162-
163-
static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
164-
{
165-
WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
166-
}
167-
168-
static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank,
169-
u32 value)
170-
{
171-
WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
172-
}
173-
174-
static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
175-
u32 value)
176-
{
177-
WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
178-
}
179-
180-
static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
181-
u32 value)
182-
{
183-
WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
184-
}
185-
186-
static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
187-
u32 value)
188-
{
189-
WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
190-
}
191-
192-
void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
193-
{
194-
csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
195-
csr_ops->read_csr_ring_head = read_csr_ring_head;
196-
csr_ops->write_csr_ring_head = write_csr_ring_head;
197-
csr_ops->read_csr_ring_tail = read_csr_ring_tail;
198-
csr_ops->write_csr_ring_tail = write_csr_ring_tail;
199-
csr_ops->read_csr_e_stat = read_csr_e_stat;
200-
csr_ops->write_csr_ring_config = write_csr_ring_config;
201-
csr_ops->write_csr_ring_base = write_csr_ring_base;
202-
csr_ops->write_csr_int_flag = write_csr_int_flag;
203-
csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
204-
csr_ops->write_csr_int_col_en = write_csr_int_col_en;
205-
csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
206-
csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
207-
csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
208-
}
209-
EXPORT_SYMBOL_GPL(adf_gen2_init_hw_csr_ops);
210-
211114
u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev)
212115
{
213116
struct adf_hw_device_data *hw_data = accel_dev->hw_device;

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