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Marek Vasuttomba
Marek Vasut
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tomba
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drm/rcar-du: dsi: Implement DSI command support
Implement support for DSI command transfer. Transmission of both Short Packet and Long Packet is implemented, so is command transmission to request response from peripheral device and transmission of non-read command with BTA. The AXI memory access mode is currently not implemented, each transfer is performed purely using controller register interface. Short Packet transfer can transfer up to 2 Bytes of data, Long Packet transfer can transfer up to 16 Bytes of data. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://lore.kernel.org/r/20250831190507.327848-1-marek.vasut+renesas@mailbox.org Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
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2 files changed

Lines changed: 350 additions & 0 deletions

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‎drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c‎

Lines changed: 225 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -937,9 +937,234 @@ static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
937937
return 0;
938938
}
939939

940+
static ssize_t rcar_mipi_dsi_host_tx_transfer(struct mipi_dsi_host *host,
941+
const struct mipi_dsi_msg *msg,
942+
bool is_rx_xfer)
943+
{
944+
const bool is_tx_long = mipi_dsi_packet_format_is_long(msg->type);
945+
struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
946+
struct mipi_dsi_packet packet;
947+
u8 payload[16] = { 0 };
948+
u32 status;
949+
int ret;
950+
951+
ret = mipi_dsi_create_packet(&packet, msg);
952+
if (ret)
953+
return ret;
954+
955+
/* Configure LP or HS command transfer. */
956+
rcar_mipi_dsi_write(dsi, TXCMSETR, (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
957+
TXCMSETR_SPDTYP : 0);
958+
959+
/* Register access mode for RX transfer. */
960+
if (is_rx_xfer)
961+
rcar_mipi_dsi_write(dsi, RXPSETR, 0);
962+
963+
/* Do not use IRQ, poll for completion, the completion is quick. */
964+
rcar_mipi_dsi_write(dsi, TXCMIER, 0);
965+
966+
/*
967+
* Send the header:
968+
* header[0] = Virtual Channel + Data Type
969+
* header[1] = Word Count LSB (LP) or first param (SP)
970+
* header[2] = Word Count MSB (LP) or second param (SP)
971+
*/
972+
rcar_mipi_dsi_write(dsi, TXCMPHDR,
973+
(is_tx_long ? TXCMPHDR_FMT : 0) |
974+
TXCMPHDR_VC(msg->channel) |
975+
TXCMPHDR_DT(msg->type) |
976+
TXCMPHDR_DATA1(packet.header[2]) |
977+
TXCMPHDR_DATA0(packet.header[1]));
978+
979+
if (is_tx_long) {
980+
memcpy(payload, packet.payload,
981+
min(msg->tx_len, sizeof(payload)));
982+
983+
rcar_mipi_dsi_write(dsi, TXCMPPD0R,
984+
(payload[3] << 24) | (payload[2] << 16) |
985+
(payload[1] << 8) | payload[0]);
986+
rcar_mipi_dsi_write(dsi, TXCMPPD1R,
987+
(payload[7] << 24) | (payload[6] << 16) |
988+
(payload[5] << 8) | payload[4]);
989+
rcar_mipi_dsi_write(dsi, TXCMPPD2R,
990+
(payload[11] << 24) | (payload[10] << 16) |
991+
(payload[9] << 8) | payload[8]);
992+
rcar_mipi_dsi_write(dsi, TXCMPPD3R,
993+
(payload[15] << 24) | (payload[14] << 16) |
994+
(payload[13] << 8) | payload[12]);
995+
}
996+
997+
/* Start the transfer, RX with BTA, TX without BTA. */
998+
if (is_rx_xfer) {
999+
rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_BTAREQ);
1000+
1001+
/* Wait until the transmission, BTA, reception completed. */
1002+
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1003+
(status & RXPSR_BTAREQEND),
1004+
2000, 50000, false, dsi, RXPSR);
1005+
} else {
1006+
rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_TXREQ);
1007+
1008+
/* Wait until the transmission completed. */
1009+
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1010+
(status & TXCMSR_TXREQEND),
1011+
2000, 50000, false, dsi, TXCMSR);
1012+
}
1013+
1014+
if (ret < 0) {
1015+
dev_err(dsi->dev, "Command transfer timeout (0x%08x)\n",
1016+
status);
1017+
return ret;
1018+
}
1019+
1020+
return packet.size;
1021+
}
1022+
1023+
static ssize_t rcar_mipi_dsi_host_rx_transfer(struct mipi_dsi_host *host,
1024+
const struct mipi_dsi_msg *msg)
1025+
{
1026+
struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
1027+
u8 *rx_buf = (u8 *)(msg->rx_buf);
1028+
u32 reg, data, status, wc;
1029+
int i, ret;
1030+
1031+
/* RX transfer received data validation and parsing starts here. */
1032+
reg = rcar_mipi_dsi_read(dsi, TOSR);
1033+
if (reg & TOSR_TATO) { /* Turn-Around TimeOut. */
1034+
/* Clear TATO Turn-Around TimeOut bit. */
1035+
rcar_mipi_dsi_write(dsi, TOSR, TOSR_TATO);
1036+
return -ETIMEDOUT;
1037+
}
1038+
1039+
reg = rcar_mipi_dsi_read(dsi, RXPSR);
1040+
1041+
if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1042+
/* Transfer with zero-length RX. */
1043+
if (!(reg & RXPSR_RCVACK)) {
1044+
/* No ACK on RX response received. */
1045+
return -EINVAL;
1046+
}
1047+
} else {
1048+
/* Transfer with non-zero-length RX. */
1049+
if (!(reg & RXPSR_RCVRESP)) {
1050+
/* No packet header of RX response received. */
1051+
return -EINVAL;
1052+
}
1053+
1054+
if (reg & (RXPSR_CRCERR | RXPSR_WCERR | RXPSR_AXIERR | RXPSR_OVRERR)) {
1055+
/* Incorrect response payload. */
1056+
return -ENODATA;
1057+
}
1058+
1059+
data = rcar_mipi_dsi_read(dsi, RXPHDR);
1060+
if (data & RXPHDR_FMT) { /* Long Packet Response. */
1061+
/* Read Long Packet Response length from packet header. */
1062+
wc = data & 0xffff;
1063+
if (wc > msg->rx_len) {
1064+
dev_warn(dsi->dev,
1065+
"Long Packet Response longer than RX buffer (%d), limited to %zu Bytes\n",
1066+
wc, msg->rx_len);
1067+
wc = msg->rx_len;
1068+
}
1069+
1070+
if (wc > 16) {
1071+
dev_warn(dsi->dev,
1072+
"Long Packet Response too long (%d), limited to 16 Bytes\n",
1073+
wc);
1074+
wc = 16;
1075+
}
1076+
1077+
for (i = 0; i < msg->rx_len; i++) {
1078+
if (!(i % 4))
1079+
data = rcar_mipi_dsi_read(dsi, RXPPD0R + i);
1080+
1081+
rx_buf[i] = data & 0xff;
1082+
data >>= 8;
1083+
}
1084+
} else { /* Short Packet Response. */
1085+
if (msg->rx_len >= 1)
1086+
rx_buf[0] = data & 0xff;
1087+
if (msg->rx_len >= 2)
1088+
rx_buf[1] = (data >> 8) & 0xff;
1089+
if (msg->rx_len >= 3) {
1090+
dev_warn(dsi->dev,
1091+
"Expected Short Packet Response too long (%zu), limited to 2 Bytes\n",
1092+
msg->rx_len);
1093+
}
1094+
}
1095+
}
1096+
1097+
if (reg & RXPSR_RCVAKE) {
1098+
/* Acknowledge and Error report received. */
1099+
return -EFAULT;
1100+
}
1101+
1102+
/* Wait until the bus handover to host processor completed. */
1103+
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1104+
!(status & PPIDL0SR_DIR),
1105+
2000, 50000, false, dsi, PPIDL0SR);
1106+
if (ret < 0) {
1107+
dev_err(dsi->dev, "Command RX DIR timeout (0x%08x)\n", status);
1108+
return ret;
1109+
}
1110+
1111+
/* Wait until the data lane is in LP11 stop state. */
1112+
ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1113+
status & PPIDL0SR_STPST,
1114+
2000, 50000, false, dsi, PPIDL0SR);
1115+
if (ret < 0) {
1116+
dev_err(dsi->dev, "Command RX STPST timeout (0x%08x)\n", status);
1117+
return ret;
1118+
}
1119+
1120+
return 0;
1121+
}
1122+
1123+
static ssize_t rcar_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
1124+
const struct mipi_dsi_msg *msg)
1125+
{
1126+
const bool is_rx_xfer = (msg->flags & MIPI_DSI_MSG_REQ_ACK) || msg->rx_len;
1127+
struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
1128+
int ret;
1129+
1130+
if (msg->tx_len > 16 || msg->rx_len > 16) {
1131+
/* ToDo: Implement Memory on AXI bus command mode. */
1132+
dev_warn(dsi->dev,
1133+
"Register-based command mode supports only up to 16 Bytes long payload\n");
1134+
return -EOPNOTSUPP;
1135+
}
1136+
1137+
ret = rcar_mipi_dsi_host_tx_transfer(host, msg, is_rx_xfer);
1138+
1139+
/* If TX transfer succeeded and this transfer has RX part. */
1140+
if (ret >= 0 && is_rx_xfer) {
1141+
ret = rcar_mipi_dsi_host_rx_transfer(host, msg);
1142+
if (ret)
1143+
return ret;
1144+
1145+
ret = msg->rx_len;
1146+
}
1147+
1148+
/*
1149+
* Wait a bit between commands, otherwise panels based on ILI9881C
1150+
* TCON may fail to correctly receive all commands sent to them.
1151+
* Until we can actually test with another DSI device, keep the
1152+
* delay here, but eventually this delay might have to be moved
1153+
* into the ILI9881C panel driver.
1154+
*/
1155+
usleep_range(1000, 2000);
1156+
1157+
/* Clear the completion interrupt. */
1158+
if (!msg->rx_len)
1159+
rcar_mipi_dsi_write(dsi, TXCMSR, TXCMSR_TXREQEND);
1160+
1161+
return ret;
1162+
}
1163+
9401164
static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
9411165
.attach = rcar_mipi_dsi_host_attach,
9421166
.detach = rcar_mipi_dsi_host_detach,
1167+
.transfer = rcar_mipi_dsi_host_transfer
9431168
};
9441169

9451170
/* -----------------------------------------------------------------------------

‎drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h‎

Lines changed: 125 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,127 @@
1515
#define TXSETR 0x100
1616
#define TXSETR_LANECNT_MASK (0x3 << 0)
1717

18+
/*
19+
* DSI Command Transfer Registers
20+
*/
21+
#define TXCMSETR 0x110
22+
#define TXCMSETR_SPDTYP (1 << 8) /* 0:HS 1:LP */
23+
#define TXCMSETR_LPPDACC (1 << 0)
24+
#define TXCMCR 0x120
25+
#define TXCMCR_BTATYP (1 << 2)
26+
#define TXCMCR_BTAREQ (1 << 1)
27+
#define TXCMCR_TXREQ (1 << 0)
28+
#define TXCMSR 0x130
29+
#define TXCMSR_CLSNERR (1 << 18)
30+
#define TXCMSR_AXIERR (1 << 16)
31+
#define TXCMSR_TXREQEND (1 << 0)
32+
#define TXCMSCR 0x134
33+
#define TXCMSCR_CLSNERR (1 << 18)
34+
#define TXCMSCR_AXIERR (1 << 16)
35+
#define TXCMSCR_TXREQEND (1 << 0)
36+
#define TXCMIER 0x138
37+
#define TXCMIER_CLSNERR (1 << 18)
38+
#define TXCMIER_AXIERR (1 << 16)
39+
#define TXCMIER_TXREQEND (1 << 0)
40+
#define TXCMADDRSET0R 0x140
41+
#define TXCMPHDR 0x150
42+
#define TXCMPHDR_FMT (1 << 24) /* 0:SP 1:LP */
43+
#define TXCMPHDR_VC(n) (((n) & 0x3) << 22)
44+
#define TXCMPHDR_DT(n) (((n) & 0x3f) << 16)
45+
#define TXCMPHDR_DATA1(n) (((n) & 0xff) << 8)
46+
#define TXCMPHDR_DATA0(n) (((n) & 0xff) << 0)
47+
#define TXCMPPD0R 0x160
48+
#define TXCMPPD1R 0x164
49+
#define TXCMPPD2R 0x168
50+
#define TXCMPPD3R 0x16c
51+
52+
#define RXSETR 0x200
53+
#define RXSETR_CRCEN (((n) & 0xf) << 24)
54+
#define RXSETR_ECCEN (((n) & 0xf) << 16)
55+
#define RXPSETR 0x210
56+
#define RXPSETR_LPPDACC (1 << 0)
57+
#define RXPSR 0x220
58+
#define RXPSR_ECCERR1B (1 << 28)
59+
#define RXPSR_UEXTRGERR (1 << 25)
60+
#define RXPSR_RESPTOERR (1 << 24)
61+
#define RXPSR_OVRERR (1 << 23)
62+
#define RXPSR_AXIERR (1 << 22)
63+
#define RXPSR_CRCERR (1 << 21)
64+
#define RXPSR_WCERR (1 << 20)
65+
#define RXPSR_UEXDTERR (1 << 19)
66+
#define RXPSR_UEXPKTERR (1 << 18)
67+
#define RXPSR_ECCERR (1 << 17)
68+
#define RXPSR_MLFERR (1 << 16)
69+
#define RXPSR_RCVACK (1 << 14)
70+
#define RXPSR_RCVEOT (1 << 10)
71+
#define RXPSR_RCVAKE (1 << 9)
72+
#define RXPSR_RCVRESP (1 << 8)
73+
#define RXPSR_BTAREQEND (1 << 0)
74+
#define RXPSCR 0x224
75+
#define RXPSCR_ECCERR1B (1 << 28)
76+
#define RXPSCR_UEXTRGERR (1 << 25)
77+
#define RXPSCR_RESPTOERR (1 << 24)
78+
#define RXPSCR_OVRERR (1 << 23)
79+
#define RXPSCR_AXIERR (1 << 22)
80+
#define RXPSCR_CRCERR (1 << 21)
81+
#define RXPSCR_WCERR (1 << 20)
82+
#define RXPSCR_UEXDTERR (1 << 19)
83+
#define RXPSCR_UEXPKTERR (1 << 18)
84+
#define RXPSCR_ECCERR (1 << 17)
85+
#define RXPSCR_MLFERR (1 << 16)
86+
#define RXPSCR_RCVACK (1 << 14)
87+
#define RXPSCR_RCVEOT (1 << 10)
88+
#define RXPSCR_RCVAKE (1 << 9)
89+
#define RXPSCR_RCVRESP (1 << 8)
90+
#define RXPSCR_BTAREQEND (1 << 0)
91+
#define RXPIER 0x228
92+
#define RXPIER_ECCERR1B (1 << 28)
93+
#define RXPIER_UEXTRGERR (1 << 25)
94+
#define RXPIER_RESPTOERR (1 << 24)
95+
#define RXPIER_OVRERR (1 << 23)
96+
#define RXPIER_AXIERR (1 << 22)
97+
#define RXPIER_CRCERR (1 << 21)
98+
#define RXPIER_WCERR (1 << 20)
99+
#define RXPIER_UEXDTERR (1 << 19)
100+
#define RXPIER_UEXPKTERR (1 << 18)
101+
#define RXPIER_ECCERR (1 << 17)
102+
#define RXPIER_MLFERR (1 << 16)
103+
#define RXPIER_RCVACK (1 << 14)
104+
#define RXPIER_RCVEOT (1 << 10)
105+
#define RXPIER_RCVAKE (1 << 9)
106+
#define RXPIER_RCVRESP (1 << 8)
107+
#define RXPIER_BTAREQEND (1 << 0)
108+
#define RXPADDRSET0R 0x230
109+
#define RXPSIZESETR 0x238
110+
#define RXPSIZESETR_SIZE(n) (((n) & 0xf) << 3)
111+
#define RXPHDR 0x240
112+
#define RXPHDR_FMT (1 << 24) /* 0:SP 1:LP */
113+
#define RXPHDR_VC(n) (((n) & 0x3) << 22)
114+
#define RXPHDR_DT(n) (((n) & 0x3f) << 16)
115+
#define RXPHDR_DATA1(n) (((n) & 0xff) << 8)
116+
#define RXPHDR_DATA0(n) (((n) & 0xff) << 0)
117+
#define RXPPD0R 0x250
118+
#define RXPPD1R 0x254
119+
#define RXPPD2R 0x258
120+
#define RXPPD3R 0x25c
121+
#define AKEPR 0x300
122+
#define AKEPR_VC(n) (((n) & 0x3) << 22)
123+
#define AKEPR_DT(n) (((n) & 0x3f) << 16)
124+
#define AKEPR_ERRRPT(n) (((n) & 0xffff) << 0)
125+
#define RXRESPTOSETR 0x400
126+
#define TACR 0x500
127+
#define TASR 0x510
128+
#define TASCR 0x514
129+
#define TAIER 0x518
130+
#define TOSR 0x610
131+
#define TOSR_TATO (1 << 2)
132+
#define TOSR_LRXHTO (1 << 1)
133+
#define TOSR_HRXTO (1 << 0)
134+
#define TOSCR 0x614
135+
#define TOSCR_TATO (1 << 2)
136+
#define TOSCR_LRXHTO (1 << 1)
137+
#define TOSCR_HRXTO (1 << 0)
138+
18139
/*
19140
* Video Mode Register
20141
*/
@@ -100,6 +221,10 @@
100221
#define PPICLSCR_HSTOLP (1 << 27)
101222
#define PPICLSCR_TOHS (1 << 26)
102223

224+
#define PPIDL0SR 0x740
225+
#define PPIDL0SR_DIR (1 << 10)
226+
#define PPIDL0SR_STPST (1 << 6)
227+
103228
#define PPIDLSR 0x760
104229
#define PPIDLSR_STPST (0xf << 0)
105230

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