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airliedairlied
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Merge tag 'amd-drm-fixes-6.19-2025-12-11' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-fixes-6.19-2025-12-11: amdgpu: - SI fix - DC reduce stack usage - HDMI fixes - VCN 4.0.5 fix - DP MST fix - DC memory allocation fix amdkfd: - SVM fix - Trap handler fix - VGPR fixes for GC 11.5 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251211195600.1641924-1-alexander.deucher@amd.com
2 parents 685f27c + 72e2445 commit 6ae7ec8

14 files changed

Lines changed: 239 additions & 138 deletions

File tree

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1069,7 +1069,9 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
10691069
}
10701070

10711071
/* Prepare a TLB flush fence to be attached to PTs */
1072-
if (!params->unlocked) {
1072+
if (!params->unlocked &&
1073+
/* SI doesn't support pasid or KIQ/MES */
1074+
params->adev->family > AMDGPU_FAMILY_SI) {
10731075
amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
10741076

10751077
/* Makes sure no PD/PT is freed before the flush */

‎drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -265,6 +265,8 @@ static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block)
265265
if (amdgpu_sriov_vf(adev))
266266
amdgpu_virt_free_mm_table(adev);
267267

268+
amdgpu_vcn_sysfs_reset_mask_fini(adev);
269+
268270
for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
269271
r = amdgpu_vcn_suspend(adev, i);
270272
if (r)

‎drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h‎

Lines changed: 36 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -3644,14 +3644,18 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = {
36443644
};
36453645

36463646
static const uint32_t cwsr_trap_gfx12_hex[] = {
3647-
0xbfa00001, 0xbfa002a2,
3648-
0xb0804009, 0xb8f8f804,
3647+
0xbfa00001, 0xbfa002b2,
3648+
0xb0804009, 0xb8eef81a,
3649+
0xbf880000, 0xb980081a,
3650+
0x00000000, 0xb8f8f804,
3651+
0x9177ff77, 0x0c000000,
3652+
0x846e9a6e, 0x8c776e77,
36493653
0x9178ff78, 0x00008c00,
36503654
0xb8fbf811, 0x8b6eff78,
36513655
0x00004000, 0xbfa10008,
36523656
0x8b6eff7b, 0x00000080,
36533657
0xbfa20018, 0x8b6ea07b,
3654-
0xbfa20042, 0xbf830010,
3658+
0xbfa2004a, 0xbf830010,
36553659
0xb8fbf811, 0xbfa0fffb,
36563660
0x8b6eff7b, 0x00000bd0,
36573661
0xbfa20010, 0xb8eef812,
@@ -3662,28 +3666,32 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
36623666
0xf0000000, 0xbfa20005,
36633667
0x8b6fff6f, 0x00000200,
36643668
0xbfa20002, 0x8b6ea07b,
3665-
0xbfa2002c, 0xbefa4d82,
3669+
0xbfa20034, 0xbefa4d82,
36663670
0xbf8a0000, 0x84fa887a,
36673671
0xbf0d8f7b, 0xbfa10002,
36683672
0x8c7bff7b, 0xffff0000,
3669-
0xf4601bbd, 0xf8000010,
3670-
0xbf8a0000, 0x846e976e,
3671-
0x9177ff77, 0x00800000,
3672-
0x8c776e77, 0xf4603bbd,
3673-
0xf8000000, 0xbf8a0000,
3674-
0xf4603ebd, 0xf8000008,
3675-
0xbf8a0000, 0x8bee6e6e,
3676-
0xbfa10001, 0xbe80486e,
3677-
0x8b6eff6d, 0xf0000000,
3678-
0xbfa20009, 0xb8eef811,
3679-
0x8b6eff6e, 0x00000080,
3680-
0xbfa20007, 0x8c78ff78,
3681-
0x00004000, 0x80ec886c,
3682-
0x82ed806d, 0xbfa00002,
3683-
0x806c846c, 0x826d806d,
3684-
0x8b6dff6d, 0x0000ffff,
3685-
0x8bfe7e7e, 0x8bea6a6a,
3686-
0x85788978, 0xb9783244,
3673+
0x8b6eff77, 0x0c000000,
3674+
0x916dff6d, 0x0c000000,
3675+
0x8c6d6e6d, 0xf4601bbd,
3676+
0xf8000010, 0xbf8a0000,
3677+
0x846e976e, 0x9177ff77,
3678+
0x00800000, 0x8c776e77,
3679+
0xf4603bbd, 0xf8000000,
3680+
0xbf8a0000, 0xf4603ebd,
3681+
0xf8000008, 0xbf8a0000,
3682+
0x8bee6e6e, 0xbfa10001,
3683+
0xbe80486e, 0x8b6eff6d,
3684+
0xf0000000, 0xbfa20009,
3685+
0xb8eef811, 0x8b6eff6e,
3686+
0x00000080, 0xbfa20007,
3687+
0x8c78ff78, 0x00004000,
3688+
0x80ec886c, 0x82ed806d,
3689+
0xbfa00002, 0x806c846c,
3690+
0x826d806d, 0x8b6dff6d,
3691+
0x0000ffff, 0x8bfe7e7e,
3692+
0x8bea6a6a, 0x85788978,
3693+
0x936eff77, 0x0002001a,
3694+
0xb96ef81a, 0xb9783244,
36873695
0xbe804a6c, 0xb8faf802,
36883696
0xbf0d987a, 0xbfa10001,
36893697
0xbfb00000, 0x8b6dff6d,
@@ -3981,7 +3989,7 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
39813989
0x008ce800, 0x00000000,
39823990
0x807d817d, 0x8070ff70,
39833991
0x00000080, 0xbf0a7b7d,
3984-
0xbfa2fff7, 0xbfa0016e,
3992+
0xbfa2fff7, 0xbfa00171,
39853993
0xbef4007e, 0x8b75ff7f,
39863994
0x0000ffff, 0x8c75ff75,
39873995
0x00040000, 0xbef60080,
@@ -4163,12 +4171,14 @@ static const uint32_t cwsr_trap_gfx12_hex[] = {
41634171
0xf8000074, 0xbf8a0000,
41644172
0x8b6dff6d, 0x0000ffff,
41654173
0x8bfe7e7e, 0x8bea6a6a,
4166-
0xb97af804, 0xbe804ec2,
4167-
0xbf94fffe, 0xbe804a6c,
4174+
0x936eff77, 0x0002001a,
4175+
0xb96ef81a, 0xb97af804,
41684176
0xbe804ec2, 0xbf94fffe,
4169-
0xbfb10000, 0xbf9f0000,
4177+
0xbe804a6c, 0xbe804ec2,
4178+
0xbf94fffe, 0xbfb10000,
41704179
0xbf9f0000, 0xbf9f0000,
41714180
0xbf9f0000, 0xbf9f0000,
4181+
0xbf9f0000, 0x00000000,
41724182
};
41734183

41744184
static const uint32_t cwsr_trap_gfx9_5_0_hex[] = {

‎drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,9 +78,16 @@ var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL
7878
var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_2_SIZE = SQ_WAVE_EXCP_FLAG_PRIV_HOST_TRAP_SHIFT - SQ_WAVE_EXCP_FLAG_PRIV_ILLEGAL_INST_SHIFT
7979
var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT = SQ_WAVE_EXCP_FLAG_PRIV_WAVE_START_SHIFT
8080
var SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SIZE = 32 - SQ_WAVE_EXCP_FLAG_PRIV_RESTORE_PART_3_SHIFT
81+
82+
var SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT = 0
83+
var SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE = 2
84+
8185
var BARRIER_STATE_SIGNAL_OFFSET = 16
8286
var BARRIER_STATE_VALID_OFFSET = 0
8387

88+
var TTMP11_SCHED_MODE_SHIFT = 26
89+
var TTMP11_SCHED_MODE_SIZE = 2
90+
var TTMP11_SCHED_MODE_MASK = 0xC000000
8491
var TTMP11_DEBUG_TRAP_ENABLED_SHIFT = 23
8592
var TTMP11_DEBUG_TRAP_ENABLED_MASK = 0x800000
8693

@@ -160,8 +167,19 @@ L_JUMP_TO_RESTORE:
160167
s_branch L_RESTORE
161168

162169
L_SKIP_RESTORE:
170+
// Assume most relaxed scheduling mode is set. Save and revert to normal mode.
171+
s_getreg_b32 ttmp2, hwreg(HW_REG_WAVE_SCHED_MODE)
172+
s_wait_alu 0
173+
s_setreg_imm32_b32 hwreg(HW_REG_WAVE_SCHED_MODE, \
174+
SQ_WAVE_SCHED_MODE_DEP_MODE_SHIFT, SQ_WAVE_SCHED_MODE_DEP_MODE_SIZE), 0
175+
163176
s_getreg_b32 s_save_state_priv, hwreg(HW_REG_WAVE_STATE_PRIV) //save STATUS since we will change SCC
164177

178+
// Save SCHED_MODE[1:0] into ttmp11[27:26].
179+
s_andn2_b32 ttmp11, ttmp11, TTMP11_SCHED_MODE_MASK
180+
s_lshl_b32 ttmp2, ttmp2, TTMP11_SCHED_MODE_SHIFT
181+
s_or_b32 ttmp11, ttmp11, ttmp2
182+
165183
// Clear SPI_PRIO: do not save with elevated priority.
166184
// Clear ECC_ERR: prevents SQC store and triggers FATAL_HALT if setreg'd.
167185
s_andn2_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_ALWAYS_CLEAR_MASK
@@ -238,6 +256,13 @@ L_FETCH_2ND_TRAP:
238256
s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA
239257
s_or_b32 ttmp15, ttmp15, 0xFFFF0000
240258
L_NO_SIGN_EXTEND_TMA:
259+
#if ASIC_FAMILY == CHIP_GFX12
260+
// Move SCHED_MODE[1:0] from ttmp11 to unused bits in ttmp1[27:26] (return PC_HI).
261+
// The second-level trap will restore from ttmp1 for backwards compatibility.
262+
s_and_b32 ttmp2, ttmp11, TTMP11_SCHED_MODE_MASK
263+
s_andn2_b32 ttmp1, ttmp1, TTMP11_SCHED_MODE_MASK
264+
s_or_b32 ttmp1, ttmp1, ttmp2
265+
#endif
241266

242267
s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 scope:SCOPE_SYS // debug trap enabled flag
243268
s_wait_idle
@@ -287,6 +312,10 @@ L_EXIT_TRAP:
287312
// STATE_PRIV.BARRIER_COMPLETE may have changed since we read it.
288313
// Only restore fields which the trap handler changes.
289314
s_lshr_b32 s_save_state_priv, s_save_state_priv, SQ_WAVE_STATE_PRIV_SCC_SHIFT
315+
316+
// Assume relaxed scheduling mode after this point.
317+
restore_sched_mode(ttmp2)
318+
290319
s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV, SQ_WAVE_STATE_PRIV_SCC_SHIFT, \
291320
SQ_WAVE_STATE_PRIV_POISON_ERR_SHIFT - SQ_WAVE_STATE_PRIV_SCC_SHIFT + 1), s_save_state_priv
292321

@@ -1043,6 +1072,9 @@ L_SKIP_BARRIER_RESTORE:
10431072
s_and_b64 exec, exec, exec // Restore STATUS.EXECZ, not writable by s_setreg_b32
10441073
s_and_b64 vcc, vcc, vcc // Restore STATUS.VCCZ, not writable by s_setreg_b32
10451074

1075+
// Assume relaxed scheduling mode after this point.
1076+
restore_sched_mode(s_restore_tmp)
1077+
10461078
s_setreg_b32 hwreg(HW_REG_WAVE_STATE_PRIV), s_restore_state_priv // SCC is included, which is changed by previous salu
10471079

10481080
// Make barrier and LDS state visible to all waves in the group.
@@ -1134,3 +1166,8 @@ function valu_sgpr_hazard
11341166
end
11351167
#endif
11361168
end
1169+
1170+
function restore_sched_mode(s_tmp)
1171+
s_bfe_u32 s_tmp, ttmp11, (TTMP11_SCHED_MODE_SHIFT | (TTMP11_SCHED_MODE_SIZE << 0x10))
1172+
s_setreg_b32 hwreg(HW_REG_WAVE_SCHED_MODE), s_tmp
1173+
end

‎drivers/gpu/drm/amd/amdkfd/kfd_queue.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -409,6 +409,7 @@ static u32 kfd_get_vgpr_size_per_cu(u32 gfxv)
409409
vgpr_size = 0x80000;
410410
else if (gfxv == 110000 || /* GFX_VERSION_PLUM_BONITO */
411411
gfxv == 110001 || /* GFX_VERSION_WHEAT_NAS */
412+
gfxv == 110501 || /* GFX_VERSION_GFX1151 */
412413
gfxv == 120000 || /* GFX_VERSION_GFX1200 */
413414
gfxv == 120001) /* GFX_VERSION_GFX1201 */
414415
vgpr_size = 0x60000;

‎drivers/gpu/drm/amd/amdkfd/kfd_svm.c‎

Lines changed: 32 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1144,30 +1144,48 @@ static int
11441144
svm_range_split_tail(struct svm_range *prange, uint64_t new_last,
11451145
struct list_head *insert_list, struct list_head *remap_list)
11461146
{
1147+
unsigned long last_align_down = ALIGN_DOWN(prange->last, 512);
1148+
unsigned long start_align = ALIGN(prange->start, 512);
1149+
bool huge_page_mapping = last_align_down > start_align;
11471150
struct svm_range *tail = NULL;
1148-
int r = svm_range_split(prange, prange->start, new_last, &tail);
1151+
int r;
11491152

1150-
if (!r) {
1151-
list_add(&tail->list, insert_list);
1152-
if (!IS_ALIGNED(new_last + 1, 1UL << prange->granularity))
1153-
list_add(&tail->update_list, remap_list);
1154-
}
1155-
return r;
1153+
r = svm_range_split(prange, prange->start, new_last, &tail);
1154+
1155+
if (r)
1156+
return r;
1157+
1158+
list_add(&tail->list, insert_list);
1159+
1160+
if (huge_page_mapping && tail->start > start_align &&
1161+
tail->start < last_align_down && (!IS_ALIGNED(tail->start, 512)))
1162+
list_add(&tail->update_list, remap_list);
1163+
1164+
return 0;
11561165
}
11571166

11581167
static int
11591168
svm_range_split_head(struct svm_range *prange, uint64_t new_start,
11601169
struct list_head *insert_list, struct list_head *remap_list)
11611170
{
1171+
unsigned long last_align_down = ALIGN_DOWN(prange->last, 512);
1172+
unsigned long start_align = ALIGN(prange->start, 512);
1173+
bool huge_page_mapping = last_align_down > start_align;
11621174
struct svm_range *head = NULL;
1163-
int r = svm_range_split(prange, new_start, prange->last, &head);
1175+
int r;
11641176

1165-
if (!r) {
1166-
list_add(&head->list, insert_list);
1167-
if (!IS_ALIGNED(new_start, 1UL << prange->granularity))
1168-
list_add(&head->update_list, remap_list);
1169-
}
1170-
return r;
1177+
r = svm_range_split(prange, new_start, prange->last, &head);
1178+
1179+
if (r)
1180+
return r;
1181+
1182+
list_add(&head->list, insert_list);
1183+
1184+
if (huge_page_mapping && head->last + 1 > start_align &&
1185+
head->last + 1 < last_align_down && (!IS_ALIGNED(head->last, 512)))
1186+
list_add(&head->update_list, remap_list);
1187+
1188+
return 0;
11711189
}
11721190

11731191
static void

‎drivers/gpu/drm/amd/amdkfd/kfd_topology.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -491,6 +491,10 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
491491
dev->node_props.num_sdma_queues_per_engine);
492492
sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
493493
dev->node_props.num_cp_queues);
494+
sysfs_show_32bit_prop(buffer, offs, "cwsr_size",
495+
dev->node_props.cwsr_size);
496+
sysfs_show_32bit_prop(buffer, offs, "ctl_stack_size",
497+
dev->node_props.ctl_stack_size);
494498

495499
if (dev->gpu) {
496500
log_max_watch_addr =

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1063,6 +1063,9 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
10631063
void amdgpu_dm_update_connector_after_detect(
10641064
struct amdgpu_dm_connector *aconnector);
10651065

1066+
void populate_hdmi_info_from_connector(struct drm_hdmi_info *info,
1067+
struct dc_edid_caps *edid_caps);
1068+
10661069
extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
10671070

10681071
int amdgpu_dm_process_dmub_aux_transfer_sync(struct dc_context *ctx, unsigned int link_index,

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -139,6 +139,9 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
139139

140140
edid_caps->edid_hdmi = connector->display_info.is_hdmi;
141141

142+
if (edid_caps->edid_hdmi)
143+
populate_hdmi_info_from_connector(&connector->display_info.hdmi, edid_caps);
144+
142145
apply_edid_quirks(dev, edid_buf, edid_caps);
143146

144147
sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
@@ -990,6 +993,11 @@ dm_helpers_read_acpi_edid(struct amdgpu_dm_connector *aconnector)
990993
return drm_edid_read_custom(connector, dm_helpers_probe_acpi_edid, connector);
991994
}
992995

996+
void populate_hdmi_info_from_connector(struct drm_hdmi_info *hdmi, struct dc_edid_caps *edid_caps)
997+
{
998+
edid_caps->scdc_present = hdmi->scdc.supported;
999+
}
1000+
9931001
enum dc_edid_status dm_helpers_read_local_edid(
9941002
struct dc_context *ctx,
9951003
struct dc_link *link,

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