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Merge tag 'amd-drm-next-6.11-2024-07-03' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.11-2024-07-03: amdgpu: - Use vmalloc for dc_state - Replay fixes - Freesync fixes - DCN 4.0.1 fixes - DML fixes - DCC updates - Misc code cleanups and bug fixes - 8K display fixes - DCN 3.5 fixes - Restructure DIO code - DML1 fixes - DML2 fixes - GFX11 fix - GFX12 updates - GFX12 modifiers fixes - RAS fixes - IP dump fixes - Add some updated IP version checks _ Silence UBSAN warning radeon: - GPUVM fix Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240703211314.2041893-1-alexander.deucher@amd.com
2 parents 71e9f40 + 4ed6a36 commit 6be146c

94 files changed

Lines changed: 624 additions & 318 deletions

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‎drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1808,6 +1808,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
18081808
case IP_VERSION(11, 0, 4):
18091809
case IP_VERSION(11, 5, 0):
18101810
case IP_VERSION(11, 5, 1):
1811+
case IP_VERSION(11, 5, 2):
18111812
amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
18121813
break;
18131814
case IP_VERSION(12, 0, 0):
@@ -1861,6 +1862,7 @@ static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
18611862
case IP_VERSION(11, 0, 4):
18621863
case IP_VERSION(11, 5, 0):
18631864
case IP_VERSION(11, 5, 1):
1865+
case IP_VERSION(11, 5, 2):
18641866
amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block);
18651867
break;
18661868
case IP_VERSION(12, 0, 0):
@@ -1962,6 +1964,7 @@ static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
19621964
case IP_VERSION(13, 0, 14):
19631965
case IP_VERSION(14, 0, 0):
19641966
case IP_VERSION(14, 0, 1):
1967+
case IP_VERSION(14, 0, 4):
19651968
amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
19661969
break;
19671970
case IP_VERSION(13, 0, 4):
@@ -2025,6 +2028,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
20252028
case IP_VERSION(14, 0, 1):
20262029
case IP_VERSION(14, 0, 2):
20272030
case IP_VERSION(14, 0, 3):
2031+
case IP_VERSION(14, 0, 4):
20282032
amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block);
20292033
break;
20302034
default:
@@ -2152,6 +2156,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
21522156
case IP_VERSION(11, 0, 4):
21532157
case IP_VERSION(11, 5, 0):
21542158
case IP_VERSION(11, 5, 1):
2159+
case IP_VERSION(11, 5, 2):
21552160
amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block);
21562161
break;
21572162
case IP_VERSION(12, 0, 0):
@@ -2207,6 +2212,7 @@ static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
22072212
case IP_VERSION(6, 0, 3):
22082213
case IP_VERSION(6, 1, 0):
22092214
case IP_VERSION(6, 1, 1):
2215+
case IP_VERSION(6, 1, 2):
22102216
amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block);
22112217
break;
22122218
case IP_VERSION(7, 0, 0):
@@ -2325,6 +2331,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
23252331
case IP_VERSION(11, 0, 4):
23262332
case IP_VERSION(11, 5, 0):
23272333
case IP_VERSION(11, 5, 1):
2334+
case IP_VERSION(11, 5, 2):
23282335
amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block);
23292336
adev->enable_mes = true;
23302337
adev->enable_mes_kiq = true;
@@ -2360,6 +2367,7 @@ static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev)
23602367
switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
23612368
case IP_VERSION(6, 1, 0):
23622369
case IP_VERSION(6, 1, 1):
2370+
case IP_VERSION(6, 1, 3):
23632371
amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block);
23642372
break;
23652373
default:
@@ -2634,6 +2642,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26342642
break;
26352643
case IP_VERSION(11, 5, 0):
26362644
case IP_VERSION(11, 5, 1):
2645+
case IP_VERSION(11, 5, 2):
26372646
adev->family = AMDGPU_FAMILY_GC_11_5_0;
26382647
break;
26392648
case IP_VERSION(12, 0, 0):
@@ -2658,6 +2667,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26582667
case IP_VERSION(11, 0, 4):
26592668
case IP_VERSION(11, 5, 0):
26602669
case IP_VERSION(11, 5, 1):
2670+
case IP_VERSION(11, 5, 2):
26612671
adev->flags |= AMD_IS_APU;
26622672
break;
26632673
default:
@@ -2696,6 +2706,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26962706
break;
26972707
case IP_VERSION(7, 11, 0):
26982708
case IP_VERSION(7, 11, 1):
2709+
case IP_VERSION(7, 11, 3):
26992710
adev->nbio.funcs = &nbio_v7_11_funcs;
27002711
adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg;
27012712
break;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c‎

Lines changed: 57 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -654,6 +654,10 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier)
654654
if (!IS_AMD_FMT_MOD(modifier))
655655
return NULL;
656656

657+
if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) < AMD_FMT_MOD_TILE_VER_GFX9 ||
658+
AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12)
659+
return NULL;
660+
657661
if (AMD_FMT_MOD_GET(DCC_RETILE, modifier))
658662
return lookup_format_info(dcc_retile_formats,
659663
ARRAY_SIZE(dcc_retile_formats),
@@ -720,32 +724,25 @@ extract_render_dcc_offset(struct amdgpu_device *adev,
720724

721725
static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb)
722726
{
723-
struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
724-
const struct drm_format_info *format_info;
725727
u64 modifier = 0;
726-
int tile = 0;
727-
int swizzle = 0;
728+
int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
728729

729-
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
730-
tile = AMD_FMT_MOD_TILE_VER_GFX12;
731-
swizzle = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE);
730+
if (!swizzle_mode) {
731+
modifier = DRM_FORMAT_MOD_LINEAR;
732+
} else {
733+
int max_comp_block =
734+
AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK);
735+
736+
modifier =
737+
AMD_FMT_MOD |
738+
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX12) |
739+
AMD_FMT_MOD_SET(TILE, swizzle_mode) |
740+
AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) |
741+
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_comp_block);
732742
}
733743

734-
modifier =
735-
AMD_FMT_MOD |
736-
AMD_FMT_MOD_SET(TILE, swizzle) |
737-
AMD_FMT_MOD_SET(TILE_VERSION, tile) |
738-
AMD_FMT_MOD_SET(DCC, 0) |
739-
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, 0);
740-
741-
format_info = amdgpu_lookup_format_info(afb->base.format->format,
742-
modifier);
743-
if (!format_info)
744-
return -EINVAL;
745-
746744
afb->base.modifier = modifier;
747745
afb->base.flags |= DRM_MODE_FB_MODIFIERS;
748-
749746
return 0;
750747
}
751748

@@ -773,12 +770,6 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
773770
int pipes = ilog2(num_pipes);
774771
uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
775772

776-
777-
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) {
778-
convert_tiling_flags_to_modifier_gfx12(afb);
779-
return 0;
780-
}
781-
782773
switch (swizzle >> 2) {
783774
case 0: /* 256B */
784775
block_size_bits = 8;
@@ -954,8 +945,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
954945
{
955946
u64 micro_tile_mode;
956947

957-
/* Zero swizzle mode means linear */
958-
if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0)
948+
if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */
959949
return 0;
960950

961951
micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
@@ -1079,6 +1069,30 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
10791069
block_width = 256 / format_info->cpp[i];
10801070
block_height = 1;
10811071
block_size_log2 = 8;
1072+
} else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) {
1073+
int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
1074+
1075+
switch (swizzle) {
1076+
case AMD_FMT_MOD_TILE_GFX12_256B_2D:
1077+
block_size_log2 = 8;
1078+
break;
1079+
case AMD_FMT_MOD_TILE_GFX12_4K_2D:
1080+
block_size_log2 = 12;
1081+
break;
1082+
case AMD_FMT_MOD_TILE_GFX12_64K_2D:
1083+
block_size_log2 = 16;
1084+
break;
1085+
case AMD_FMT_MOD_TILE_GFX12_256K_2D:
1086+
block_size_log2 = 18;
1087+
break;
1088+
default:
1089+
drm_dbg_kms(rfb->base.dev,
1090+
"Gfx12 swizzle mode with unknown block size: %d\n", swizzle);
1091+
return -EINVAL;
1092+
}
1093+
1094+
get_block_dimensions(block_size_log2, format_info->cpp[i],
1095+
&block_width, &block_height);
10821096
} else {
10831097
int swizzle = AMD_FMT_MOD_GET(TILE, modifier);
10841098

@@ -1114,7 +1128,8 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
11141128
return ret;
11151129
}
11161130

1117-
if (AMD_FMT_MOD_GET(DCC, modifier)) {
1131+
if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 &&
1132+
AMD_FMT_MOD_GET(DCC, modifier)) {
11181133
if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) {
11191134
block_size_log2 = get_dcc_block_size(modifier, false, false);
11201135
get_block_dimensions(block_size_log2 + 8, format_info->cpp[0],
@@ -1144,14 +1159,16 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb)
11441159
}
11451160

11461161
static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
1147-
uint64_t *tiling_flags, bool *tmz_surface)
1162+
uint64_t *tiling_flags, bool *tmz_surface,
1163+
bool *gfx12_dcc)
11481164
{
11491165
struct amdgpu_bo *rbo;
11501166
int r;
11511167

11521168
if (!amdgpu_fb) {
11531169
*tiling_flags = 0;
11541170
*tmz_surface = false;
1171+
*gfx12_dcc = false;
11551172
return 0;
11561173
}
11571174

@@ -1165,11 +1182,9 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb
11651182
return r;
11661183
}
11671184

1168-
if (tiling_flags)
1169-
amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1170-
1171-
if (tmz_surface)
1172-
*tmz_surface = amdgpu_bo_encrypted(rbo);
1185+
amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
1186+
*tmz_surface = amdgpu_bo_encrypted(rbo);
1187+
*gfx12_dcc = rbo->flags & AMDGPU_GEM_CREATE_GFX12_DCC;
11731188

11741189
amdgpu_bo_unreserve(rbo);
11751190

@@ -1238,7 +1253,8 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev,
12381253
}
12391254
}
12401255

1241-
ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface);
1256+
ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface,
1257+
&rfb->gfx12_dcc);
12421258
if (ret)
12431259
return ret;
12441260

@@ -1252,7 +1268,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev,
12521268

12531269
if (!dev->mode_config.fb_modifiers_not_supported &&
12541270
!(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) {
1255-
ret = convert_tiling_flags_to_modifier(rfb);
1271+
if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0))
1272+
ret = convert_tiling_flags_to_modifier_gfx12(rfb);
1273+
else
1274+
ret = convert_tiling_flags_to_modifier(rfb);
1275+
12561276
if (ret) {
12571277
drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier",
12581278
rfb->tiling_flags);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -848,6 +848,7 @@ void amdgpu_gmc_tmz_set(struct amdgpu_device *adev)
848848
case IP_VERSION(11, 0, 4):
849849
case IP_VERSION(11, 5, 0):
850850
case IP_VERSION(11, 5, 1):
851+
case IP_VERSION(11, 5, 2):
851852
/* Don't enable it by default yet.
852853
*/
853854
if (amdgpu_tmz < 1) {

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,7 @@ struct amdgpu_framebuffer {
300300

301301
uint64_t tiling_flags;
302302
bool tmz_surface;
303+
bool gfx12_dcc;
303304

304305
/* caching for later use */
305306
uint64_t address;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,6 +219,7 @@ static int psp_early_init(void *handle)
219219
case IP_VERSION(13, 0, 11):
220220
case IP_VERSION(14, 0, 0):
221221
case IP_VERSION(14, 0, 1):
222+
case IP_VERSION(14, 0, 4):
222223
psp_v13_0_set_psp_funcs(psp);
223224
psp->boot_time_tmr = false;
224225
break;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4565,7 +4565,7 @@ static void amdgpu_ras_boot_time_error_reporting(struct amdgpu_device *adev,
45654565

45664566
socket_id = AMDGPU_RAS_GPU_ERR_SOCKET_ID(boot_error);
45674567
aid_id = AMDGPU_RAS_GPU_ERR_AID_ID(boot_error);
4568-
hbm_id = AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error);
4568+
hbm_id = ((1 == AMDGPU_RAS_GPU_ERR_HBM_ID(boot_error)) ? 0 : 1);
45694569

45704570
if (AMDGPU_RAS_GPU_ERR_MEM_TRAINING(boot_error))
45714571
dev_info(adev->dev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -302,6 +302,7 @@ static int vpe_early_init(void *handle)
302302

303303
switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
304304
case IP_VERSION(6, 1, 0):
305+
case IP_VERSION(6, 1, 3):
305306
vpe_v6_1_set_funcs(vpe);
306307
break;
307308
case IP_VERSION(6, 1, 1):

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9287,6 +9287,7 @@ static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
92879287
if (!adev->gfx.ip_dump_gfx_queues)
92889288
return;
92899289

9290+
index = 0;
92909291
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
92919292
drm_printf(p, "\nnum_me: %d num_pipe: %d num_queue: %d\n",
92929293
adev->gfx.me.num_me,
@@ -9352,6 +9353,7 @@ static void gfx_v10_ip_dump(void *handle)
93529353
if (!adev->gfx.ip_dump_gfx_queues)
93539354
return;
93549355

9356+
index = 0;
93559357
reg_count = ARRAY_SIZE(gc_gfx_queue_reg_list_10);
93569358
amdgpu_gfx_off_ctrl(adev, false);
93579359
mutex_lock(&adev->srbm_mutex);

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