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Srinivas Kandagatlavinodkoul
Srinivas Kandagatla
authored and
vinodkoul
committed
soundwire: qcom: prepare for v3.x
cleanup the register layout structs to prepare for adding new 3.x controller support. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> Tested-by: Alexey Klimov <alexey.klimov@linaro.org> # sm8550 Link: https://patch.msgid.link/20250912083225.228778-6-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
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Lines changed: 56 additions & 21 deletions

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‎drivers/soundwire/qcom.c‎

Lines changed: 56 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -99,14 +99,15 @@
9999
#define SWRM_MCP_SLV_STATUS 0x1090
100100
#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
101101
#define SWRM_MCP_SLV_STATUS_SZ 2
102-
#define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103-
#define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104-
#define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105-
#define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106-
#define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107-
#define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108-
#define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109-
#define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
102+
103+
#define SWRM_DPn_PORT_CTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
104+
#define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
105+
#define SWRM_DPn_BLOCK_CTRL_1(offset, n) (offset + 0x100 * (n - 1))
106+
#define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
107+
#define SWRM_DPn_PORT_HCTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
108+
#define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
109+
#define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
110+
110111
#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111112
#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
112113

@@ -171,6 +172,13 @@ enum {
171172
SWRM_REG_CMD_FIFO_RD_CMD,
172173
SWRM_REG_CMD_FIFO_STATUS,
173174
SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
175+
SWRM_OFFSET_DP_PORT_CTRL_BANK,
176+
SWRM_OFFSET_DP_PORT_CTRL_2_BANK,
177+
SWRM_OFFSET_DP_BLOCK_CTRL_1,
178+
SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,
179+
SWRM_OFFSET_DP_PORT_HCTRL_BANK,
180+
SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,
181+
SWRM_OFFSET_DP_SAMPLECTRL2_BANK,
174182
};
175183

176184
struct qcom_swrm_ctrl {
@@ -230,6 +238,13 @@ static const unsigned int swrm_v1_3_reg_layout[] = {
230238
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
231239
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
232240
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
241+
[SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
242+
[SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
243+
[SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
244+
[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
245+
[SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
246+
[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
247+
[SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
233248
};
234249

235250
static const struct qcom_swrm_data swrm_v1_3_data = {
@@ -264,6 +279,13 @@ static const unsigned int swrm_v2_0_reg_layout[] = {
264279
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
265280
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
266281
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
282+
[SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
283+
[SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
284+
[SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
285+
[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
286+
[SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
287+
[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
288+
[SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
267289
};
268290

269291
static const struct qcom_swrm_data swrm_v2_0_data = {
@@ -964,10 +986,10 @@ static int qcom_swrm_port_params(struct sdw_bus *bus,
964986
unsigned int bank)
965987
{
966988
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
989+
u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];
967990

968-
return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
969-
p_params->bps - 1);
970-
991+
return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num),
992+
p_params->bps - 1);
971993
}
972994

973995
static int qcom_swrm_transport_params(struct sdw_bus *bus,
@@ -977,9 +999,11 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus,
977999
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
9781000
struct qcom_swrm_port_config *pcfg;
9791001
u32 value;
980-
int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
1002+
int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
9811003
int ret;
9821004

1005+
reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);
1006+
9831007
pcfg = &ctrl->pconfig[params->port_num];
9841008

9851009
value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
@@ -991,36 +1015,43 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus,
9911015
goto err;
9921016

9931017
if (pcfg->si > 0xff) {
1018+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];
9941019
value = (pcfg->si >> 8) & 0xff;
995-
reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
1020+
reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);
1021+
9961022
ret = ctrl->reg_write(ctrl, reg, value);
9971023
if (ret)
9981024
goto err;
9991025
}
10001026

10011027
if (pcfg->lane_control != SWR_INVALID_PARAM) {
1002-
reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
1028+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];
1029+
reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);
1030+
10031031
value = pcfg->lane_control;
10041032
ret = ctrl->reg_write(ctrl, reg, value);
10051033
if (ret)
10061034
goto err;
10071035
}
10081036

10091037
if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1010-
reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
1038+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];
1039+
1040+
reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);
1041+
10111042
value = pcfg->blk_group_count;
10121043
ret = ctrl->reg_write(ctrl, reg, value);
10131044
if (ret)
10141045
goto err;
10151046
}
10161047

1017-
if (pcfg->hstart != SWR_INVALID_PARAM
1018-
&& pcfg->hstop != SWR_INVALID_PARAM) {
1019-
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1048+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];
1049+
reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);
1050+
1051+
if (pcfg->hstart != SWR_INVALID_PARAM && pcfg->hstop != SWR_INVALID_PARAM) {
10201052
value = (pcfg->hstop << 4) | pcfg->hstart;
10211053
ret = ctrl->reg_write(ctrl, reg, value);
10221054
} else {
1023-
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
10241055
value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
10251056
ret = ctrl->reg_write(ctrl, reg, value);
10261057
}
@@ -1029,7 +1060,8 @@ static int qcom_swrm_transport_params(struct sdw_bus *bus,
10291060
goto err;
10301061

10311062
if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1032-
reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
1063+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];
1064+
reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);
10331065
ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
10341066
}
10351067

@@ -1041,9 +1073,12 @@ static int qcom_swrm_port_enable(struct sdw_bus *bus,
10411073
struct sdw_enable_ch *enable_ch,
10421074
unsigned int bank)
10431075
{
1044-
u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
1076+
u32 reg;
10451077
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
10461078
u32 val;
1079+
u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1080+
1081+
reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);
10471082

10481083
ctrl->reg_read(ctrl, reg, &val);
10491084

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